> Hi.
>
> The patch comes up with new summaries that use vector as underlying
> data structure. In order to make the code more readable I decided to
> factor out some common code into base classes.
>
> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
> I tested building Inks
Hi.
The patch handles an undefined behavior caused by 1U << 32 shift
for an integer type.
Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
Ready to be installed?
Thanks,
Martin
libcpp/ChangeLog:
2019-02-18 Martin Liska
PR c++/89383
* line-map.c (linema
On Sun, Feb 17, 2019 at 8:19 PM Thomas Koenig wrote:
>
> Hello world,
>
> the attached patch fixes a rather bad ABI violation on POWER systems.
>
> In the absence of an explicit interface and if a procedure is not in
> the same file, gfortran currently generates wrong function decls -
> a longstan
On Mon, Feb 18, 2019 at 09:46:33AM +0100, Martin Liška wrote:
> Hi.
>
> The patch handles an undefined behavior caused by 1U << 32 shift
> for an integer type.
That will still ICE on 32-bit hosts, won't it?
So, either you need ((uint64_t) 1) << ..., or column_bits && ... >= ...
> 2019-02-18 Mar
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we don't see an initializer we believe we are surely dealing
with a case of C++17 template argument deduction for class templates,
but, in fact, it's just an ill-formed C++14 template variable
specialization. Conveniently, we can use her
On 2/18/19 9:54 AM, Jakub Jelinek wrote:
> On Mon, Feb 18, 2019 at 09:46:33AM +0100, Martin Liška wrote:
>> Hi.
>>
>> The patch handles an undefined behavior caused by 1U << 32 shift
>> for an integer type.
>
> That will still ICE on 32-bit hosts, won't it?
> So, either you need ((uint64_t) 1) <<
On 16.02.19 18:52, Jakub Jelinek wrote:
> Hi!
>
> While looking into PR89369, I've noticed various spots in s390.md
> using 1ul or 1UL which might not work properly if the host is e.g. ilp32,
> even even instead of using ULL constants it is better to use
> HOST_WIDE_INT_* macros for HOST_WIDE_INT
On Tue, Feb 12, 2019 at 2:13 AM Martin Sebor wrote:
>
> The attached patch removes the assumption introduced earlier today
> in my fix for bug 87996 that the valid_constant_size_p argument is
> a constant expression. I couldn't come up with a C/C++ test case
> where this isn't true but apparently
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we don't see an initializer we believe we are surely
dealing with a case of C++17 template argument deduction for class
templates, but, in fact, it's just an ill-formed C++14 template
v
Hi Ian,
> This patch to the libgo gotest script runs examples when appropriate
> in the libgo testsuite. An example with a "// Output:" comment is
> supposed to be run, comparing the output of the example with the text
> in the comment. Up until now we were not actually doing that, so we
> were
On Feb 18 2019, Rainer Orth wrote:
> diff --git a/libgo/testsuite/gotest b/libgo/testsuite/gotest
> --- a/libgo/testsuite/gotest
> +++ b/libgo/testsuite/gotest
> @@ -627,13 +627,13 @@ symtogo() {
>-e 's/[]*$/\\n/g' |
>tr -d '
Hi Ian,
> On Fri, Feb 15, 2019 at 4:03 AM Rainer Orth
> wrote:
>>
>> Andreas Schwab writes:
>>
>> > This breaks non-split-stack builds.
>> >
>> > ../../../libgo/runtime/stack.c: In function 'doscanstack1':
>> > ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of
>> > 'scanstackb
Hi Andreas,
> On Feb 18 2019, Rainer Orth wrote:
>
>> diff --git a/libgo/testsuite/gotest b/libgo/testsuite/gotest
>> --- a/libgo/testsuite/gotest
>> +++ b/libgo/testsuite/gotest
>> @@ -627,13 +627,13 @@ symtogo() {
>> -e 's/[]*$/\\n/g' |
>>
On 16.02.19 18:49, Jakub Jelinek wrote:
> Hi!
>
> If S390_USE_TARGET_ATTRIBUTE is 0 (e.g. because of configuring against old
> binutils or even with no binutils at all), then indirect jumps are emitted
> unconditionally, no matter what is selected on the command line, including
> the default optio
On 16.02.19 19:38, Jakub Jelinek wrote:
> Hi!
>
> The following patch fixes wrong-code on the following testcase extracted
> from pseudo-RNG with e.g. -march=zEC12 -O2.
> The problem is in the instruction emitted by the *rsbg_sidi_srl
> patterns. We have in *.final correct:
> (insn 67 65 68 (para
Two additional reports:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89384
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89385
There are further problems I observed, but I consider it likely that there are
significant interactions with the needed fixes for reported bugs,
so would keep these i
PING^1
On 11/30/18 11:26 AM, Martin Liška wrote:
> Hi Jason.
>
> Just small nits I noticed for:
>
> cat test4.C
> int a, b, c;
>
> void
> __attribute__((noinline))
> bar()
> {
> if (a == 123)
> [[likely]] c = 5;
> else
> [[likely]] b = 77;
> }
>
> int main()
> {
> bar ();
> ret
On 2/17/19 7:29 AM, Jakub Jelinek wrote:
On Mon, Feb 11, 2019 at 12:08:32PM +0100, Jakub Jelinek wrote:
So like the patch below (though, I have only limited possibilities to test
this, can throw it in armv7hl-linux-gnueabi distro build).
Actually, that patch was bad, I misread the CORE_REGS v
On Sun, Feb 17, 2019 at 7:19 PM Thomas Koenig wrote:
>
> Hello world,
>
> the attached patch fixes a rather bad ABI violation on POWER systems.
>
> In the absence of an explicit interface and if a procedure is not in
> the same file, gfortran currently generates wrong function decls -
> a longstan
no-warning overloading means we should be quite narrow to catch only
problematic cases when setting the flag.
Bootstrapped and tested on x86_64-unknown-linux-gnu, applied to trunk.
Richard.
2019-02-18 Richard Biener
PR tree-optimization/89296
* tree-ssa-loop-ch.c (ch_base::
On Sat, Feb 16, 2019 at 11:46 PM H.J. Lu wrote:
>
> From: Uros Bizjak
>
> 2019-02-14 Uroš Bizjak
>
> PR target/89021
> * config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
> * config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto.
> (*vec_concatv2sf_ss
On Mon, Feb 18, 2019 at 2:51 PM Richard Biener
wrote:
> The patch looks good to me. I wonder how the frontend handles
> the 2nd call to doesntwork_p8 for
>
> program main
> implicit none
> character :: c
> character(len=20) :: res, doesntwork_p8
> external do
On 11/27/18 10:11 PM, Thomas Koenig wrote:
> Am 27.11.18 um 17:22 schrieb Steve Ellcey:
>> Why wouldn't clang (flang) want to use the same mechanism as
>> GCC/gfortran? I know there is some interest/work going on here for
>> flang and we would like a consistent way to use pre-includes to define
>>
On 17.02.19 17:07, Iain Buclaw wrote:
> On Sat, 16 Feb 2019 at 13:44, Matthias Klose wrote:
>>
>> On 12.02.19 21:54, Iain Buclaw wrote:
>>> On Tue, 12 Feb 2019 at 10:40, Richard Biener
>>> wrote:
On Sat, Feb 9, 2019 at 10:37 AM Iain Buclaw wrote:
>
> On Mon, 28 Jan 2019 at 13:
On Sat, 16 Feb 2019, Jakub Jelinek wrote:
> On Sat, Feb 16, 2019 at 12:10:22PM +0100, Richard Biener wrote:
> > On February 16, 2019 8:12:34 AM GMT+01:00, Jakub Jelinek
> > wrote:
> > >Both the C and C++ standard guarantee that the argc argument to main is
> > >non-negative, the following patch
Hi Iain,
>> > I'd say go for it. I see that there's a tab that found its way into
>> > lib/gdc.exp, and there's a copyright notice that needs fixing up.
>>
>> that tab is both due the gcc convention (GCS actually) of using tabs
>> instead of 8 spaces, unlike D, and Emacs' tcl mode that follows it
Some recently added libstdc++ filesystem tests are missing a
dg-require-filesystem-ts.
Committed as obvious.
ChangeLog:
2019-02-16 Wilco Dijkstra
* 27_io/filesystem/operations/all.cc: Add dg-require-filesystem-ts.
* 27_io/filesystem/operations/resize_file.cc: Likewise.
Fix pr88680.C failures due to short enums on arm-none-eabi.
Committed as obvious.
ChangeLog:
2019-02-18 Wilco Dijkstra
* g++.dg/wrappers/pr88680.C: Add -fno-short-enums.
--
diff --git a/gcc/testsuite/g++.dg/wrappers/pr88680.C
b/gcc/testsuite/g++.dg/wrappers/pr88680.C
index
5497cda5
On Sun, Feb 17, 2019 at 12:46 PM H.J. Lu wrote:
>
> On Sun, Feb 17, 2019 at 10:49 AM Uros Bizjak wrote:
> >
> > On Sun, Feb 17, 2019 at 6:37 PM H.J. Lu wrote:
> >
> > > > > > > > > > On x86-64, since __m64 is returned and passed in XMM
> > > > > > > > > > registers, we can
> > > > > > > > > > e
On Mon, Feb 18, 2019 at 3:22 PM H.J. Lu wrote:
> > > > > > > > > > > On x86-64, since __m64 is returned and passed in XMM
> > > > > > > > > > > registers, we can
> > > > > > > > > > > emulate MMX intrinsics with SSE instructions. To support
> > > > > > > > > > > it, we added
> > > > > > > > > >
Handle stack pointer with SUBS/ADDS instructions.
In general the stack pointer was not handled for many SUBS/ADDS patterns in
aarch64.md.
Both the "extended register" and "immediate" forms allow the stack pointer to be
used as the source register, while no form allows the stack pointer for the
des
On Mon, Feb 18, 2019 at 6:37 AM Uros Bizjak wrote:
>
> On Mon, Feb 18, 2019 at 3:22 PM H.J. Lu wrote:
>
> > > > > > > > > > > > On x86-64, since __m64 is returned and passed in XMM
> > > > > > > > > > > > registers, we can
> > > > > > > > > > > > emulate MMX intrinsics with SSE instructions. To
The code in emit_case_dispatch_table() will very clearly always emit
branch/label/jumptable_data/barrier
so this does need to be handled. So, yes tablejump always looks like this, and
also yes it seems to be
ripe ground for logic bugs, we have 88308, 88347, 88423 all related to it.
In the long t
On Mon, 18 Feb 2019, Aaron Sawdey wrote:
> The code in emit_case_dispatch_table() will very clearly always emit
> branch/label/jumptable_data/barrier
> so this does need to be handled. So, yes tablejump always looks like this,
> and also yes it seems to be
> ripe ground for logic bugs, we have 8
Ping: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00361.html
On 2/6/19 5:28 PM, Martin Sebor wrote:
Recent libgcc builds have been triggering -Wbuiltin-declaration-mismatch
due to the declaration of the __clear_cache built-in being incompatible
with how GCC declares it internally. The attache
On Mon, Feb 18, 2019 at 10:48:35AM +0200, Janne Blomqvist wrote:
> I wonder if we shouldn't exorcise all the varargs stuff, it seems to
> cause more problems than benefits? But not in stage4 if we can avoid
> it..
On the Power ABIs at least, unprototyped functions (a K&R thing for C) are
handled t
On 2/18/19 5:31 AM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we don't see an initializer we believe we are surely
dealing with a case of C++17 template argument deduction for class
templates, but, in fact,
On 2/18/19 10:41 AM, Alexander Monakov wrote:
> On Mon, 18 Feb 2019, Aaron Sawdey wrote:
>
>> The code in emit_case_dispatch_table() will very clearly always emit
>> branch/label/jumptable_data/barrier
>> so this does need to be handled. So, yes tablejump always looks like this,
>> and also ye
I have now committed the patch as r268992. Janne and Richard, thanks
for the review and the comments.
Am 18.02.19 um 13:50 schrieb Richard Biener:
On Sun, Feb 17, 2019 at 7:19 PM Thomas Koenig wrote:
Regression tests turned up a few ICEs (now fixed), plus two
very invalid test cases, which I
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_3): Likewise.
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c (i
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
source operand is allowed.
2019-02-08 H.J. Lu
Uros Bizjak
PR target/89021
* config/i386/i386-protos.h (ix86_move_vec
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
prototype.
* config/i386/i38
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
---
gcc/c
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 25 +++
On x86-64, since __m64 is returned and passed in XMM registers, we can
emulate MMX intrinsics with SSE instructions. To support it, we added
#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
;; Define instruction set of MMX instructions
(define_attr "mmx_isa" "base,native,x64,x64_noavx,x
Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt3): Likewise.
---
Emulate MMX 3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:mmx_3): Also allow
TARGET_MMX_WITH_SSE.
(any_logic:3): New.
(any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
---
Emulate MMX ashr3/3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr3): Also allow
TARGET_MMX_WITH_SSE. Add SSE emulation.
(mmx_3): Likewise.
(ashr3): New.
(3): Likewise.
---
gcc/config/i386/mmx
Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.
PR target/89021
* config/i386/constraints.md (Yw): New constraint.
* config/i386/mmx.md (*vec_
Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 del
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_mulv4hi3): Also allow
TARGET_MMX_WITH_SSE.
(mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
---
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (sse_cvtpi2ps): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/m
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
PR target/89021
* config/i386/sse.md (sse_cvtps2pi): Add SSE emulation.
(sse_cvttps2pi): Likewise.
---
gcc/config/i386/sse.md | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX
or TARGET_MMX_WITH_SSE.
(*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
gcc/config/i386/sse.md | 26
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
gcc/config/i3
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split a
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
without MMX.
PR target/89021
* config/i386/mmx.md (mmx_): Renamed to ...
(*mmx_): This.
(mmx_): New expander.
---
gcc/config/i386/mmx.md | 30 +-
1 file changed, 29
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
* config/i386/i386-builtin.
On 2/15/19 8:30 PM, Sandra Loosemore wrote:
On 2/13/19 2:46 PM, Martin Sebor wrote:
The attached patch adds documentation for the __has_attribute (and
__has_cpp_attribute) and __has_include operators added in r215752.
Thanks!
I was a little unsure where to add this, whether the preprocessor
On 2/16/19 12:12 AM, Jakub Jelinek wrote:
Hi!
Both the C and C++ standard guarantee that the argc argument to main is
non-negative, the following patch sets (or adjusts) the corresponding
SSA_NAME_RANGE_INFO. While main is just one, with IPA VRP it can also
propagate etc. I had to change one t
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i3
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
define_insn_an
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 26 -
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/
Emulate MMX abs2 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/sse.md (abs2): Add SSE emulation.
---
gcc/config/i386/sse.md | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/conf
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(*mmx_uavgv8qi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 25 +
From: Uros Bizjak
2019-02-18 Uroš Bizjak
PR target/89021
* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
* config/i386/sse.md (sse2_cvtpi2pd): Ditto.
(sse2_cvtpd2pi): Ditto.
(sse2_cvttpd2pi): Ditto.
(*vec_concatv2sf_sse4_1): Di
Emulate MMX movntq with SSE2 movntidi. Only register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (sse_movntq): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386/mmx
PR target/89021
* config/i386/mmx.md (*vec_dupv2sf): Changed to
define_insn_and_split to support SSE emulation.
(*vec_extractv2sf_0): Likewise.
(*vec_extractv2sf_1): Likewise.
(*vec_extractv2si_0): Likewise.
(*vec_extractv2si_1): Likewise.
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
---
gcc/config/i38
Emulate MMX mmx_pinsrw with SSE. Only SSE register destination operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_pinsrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 33 +
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. A
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/xmmintrin.h: Em
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_v8qi3): Likewise.
(smaxmin:v4hi3): New.
(umaxmin:v8qi3
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/con
PR target/89021
* config/i386/mmx.md (MMXMODE:mov): Also allow
TARGET_MMX_WITH_SSE.
(MMXMODE:*mov_internal): Likewise.
(MMXMODE:movmisalign): Likewise.
---
gcc/config/i386/mmx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/c
On 2/15/19 9:01 PM, Sandra Loosemore wrote:
On 2/13/19 4:33 PM, Martin Sebor wrote:
Index: gcc/doc/extend.texi
===
--- gcc/doc/extend.texi (revision 268856)
+++ gcc/doc/extend.texi (working copy)
@@ -12890,6 +12890,22 @@ buil
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_uavgv4hi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 26 +
Description: fixed a couple of typos in testsuite/README.
Testing: make dvi, make info, although I doubt needed.
svn diff (with -up) yields:
Index: gcc/testsuite/README
===
--- gcc/testsuite/README(revision 268955)
+++ gcc/tes
On 2/18/19 7:44 AM, Martin Liška wrote:
PING^1
On 11/30/18 11:26 AM, Martin Liška wrote:
Hi Jason.
Just small nits I noticed for:
cat test4.C
int a, b, c;
void
__attribute__((noinline))
bar()
{
if (a == 123)
[[likely]] c = 5;
else
[[likely]] b = 77;
}
int main()
{
bar ();
On Mon, Feb 18, 2019 at 2:48 AM Rainer Orth
wrote:
>
> > The code was already calling syscall, it was just doing it in a way
> > that the types didn't necessarily match the C declaration. This is
> > the implementation of Go's syscall.Syscall function, so there isn't
> > really anything else we
On 2/14/19 7:23 AM, Tom Tromey wrote:
>> "Marc" == Marc Glisse writes:
>
>>> Lastly, in the case of uninitialized variables, the usual solution
>>> of initializing them is trivial and always safe (some coding styles
>>> even require it).
>
> Marc> Here it shows that we don't work with the sa
Hi Christophe,
> dg-extract-results currently moves lines like
> WARNING: program timed out
> at the end of each .exp section when it generates .sum files.
>
> This is because it sorts its output based on the 2nd field, which is
> normally the testname as in:
> FAIL: gcc.c-torture/execute/20020129
On 2/4/19 3:52 PM, Martin Jambor wrote:
> Hi,
>
> On Mon, Feb 04 2019, Marc Glisse wrote:
>> On Mon, 4 Feb 2019, Martin Sebor wrote:
>>>
>
> ...
>
>>> You're right that this is hard to imagine without first hand experience
>>> with the problem. If this is a common pattern with the warning in C+
Hi Jakub,
>> The following testcase is miscompiled on x86_64-linux (-m32 and -m64) at
>> -O1, as a pointer has two vars in points-to set, the first one is escaped
>> heap var and the second one is escaped non-heap var, and in the end the last
>> var that sets vars_contains_escaped won and overwrot
On Mon, Feb 18, 2019 at 7:25 PM Segher Boessenkool <
seg...@kernel.crashing.org> wrote:
> On Mon, Feb 18, 2019 at 10:48:35AM +0200, Janne Blomqvist wrote:
> > I wonder if we shouldn't exorcise all the varargs stuff, it seems to
> > cause more problems than benefits? But not in stage4 if we can avo
On Mon, Feb 18, 2019 at 09:15:39PM +0100, Rainer Orth wrote:
> 2019-02-15 Rainer Orth
>
> * g++.dg/torture/pr89303.C (bad_weak_ptr): Rename to
> bad_weak_ptr_.
Ok, thanks.
If needed, guess we could rename much more (or rename the namespace in which
most of it is from std to my_std,
Hi Janne,
I'm not really sure if there is any good reason why GFortran occasionally
generates these varargs declarations, hence my suggestion to get rid of
them. Unless the middle-end is planning to get rid of untyped function
decls?
Are they still being generated after the patch went in? I'm
On Mon, Feb 18, 2019 at 10:30 PM Thomas Koenig
wrote:
> Hi Janne,
>
> > I'm not really sure if there is any good reason why GFortran occasionally
> > generates these varargs declarations, hence my suggestion to get rid of
> > them. Unless the middle-end is planning to get rid of untyped function
Sharon Dvir writes:
> Description: fixed a couple of typos in testsuite/README.
> Testing: make dvi, make info, although I doubt needed.
Applied, thanks.
Richard
Martin Sebor writes:
> Recent libgcc builds have been triggering -Wbuiltin-declaration-mismatch
> due to the declaration of the __clear_cache built-in being incompatible
> with how GCC declares it internally. The attached patch adjusts
> the libgcc declaration and the one in the manual to match w
On 2/17/19 11:54 AM, Marek Polacek wrote:
On Sat, Feb 16, 2019 at 03:54:21PM -0500, Marek Polacek wrote:
I noticed this test fails in c++2a since the implementation of P0846
landed in r265734. Since it's in g++.old-deja/, I never noticted the
fail (but I don't see any others). This patch tweak
Hi Bernd,
Am 16.02.19 um 13:58 schrieb Bernd Edlinger:
So here is the latest version with the requested change.
How is the procedure with libpobos patches?
Can we check them into the gcc svn, or will Ian have to
push them first into the upstream?
Most phobos/druntime changes should be upstre
Hello world,
this patch fixes the 9 regression in C interop with contiguous
arguments recently reported by Reinhold Bader.
ChangeLog and patch say it all. I hope I didn't overlook any
obvious things here (Paul, maybe you can take a look).
Regression-tested. OK for trunk?
Regards
Thom
Hi Jason,
On 18/02/19 19:28, Jason Merrill wrote:
On 2/18/19 5:31 AM, Paolo Carlini wrote:
Hi Jason,
On 18/02/19 10:20, Jason Merrill wrote:
On 2/17/19 6:58 AM, Paolo Carlini wrote:
Hi,
here, when we don't see an initializer we believe we are surely
dealing with a case of C++17 template ar
1 - 100 of 129 matches
Mail list logo
