On Fri, Feb 15, 2019 at 3:48 PM Jakub Jelinek wrote:
>
> On Fri, Feb 15, 2019 at 08:33:44AM +0100, Jakub Jelinek wrote:
> > On Fri, Feb 15, 2019 at 03:25:33PM +0800, Bin.Cheng wrote:
> > > So with what condition we can safely rewrite trapping operations into
> > > non trapping one? Does the rewri
This breaks non-split-stack builds.
../../../libgo/runtime/stack.c: In function 'doscanstack1':
../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of
'scanstackblock' makes integer from pointer without a cast
[-Werror=int-conversion]
113 | scanstackblock(bottom, (uintptr)(top -
On Thu, 14 Feb 2019 at 17:52, Tamar Christina wrote:
>
> Hi Kyrill,
>
> I couldn't find a way to actually generate this case so I have instead removed
> the entry from ANY128. New patch and changelog below.
>
> --
>
> The iterator ANY64 are used in various general split patterns and is supposed
>
Hi,
this is a regression present on all active branches since the controversial
get_initial_register_offset stuff was added to rtlanal.c some time ago, and
visible in the testsuite on PowerPC/Linux under the form of gnat.dg/opt73.adb
timing out at run time.
The problem is that the compiler gen
This adjusts the compiler to the assembler change I recently istalled:
https://sourceware.org/ml/binutils/2019-02/msg00035.html
The final.c one-liner is trivial, it changes the test to the exact condition
under which the fallthrough code won't segfault.
Tested on visium-elf, applied on the mai
The only interesting one is gcc.dg/tree-ssa/pr84859.c: for it to pass, the
undocumented -ftree-cselim must be enabled, which is done automatically only
on targets with conditional moves, what the Visium is not.
Tested on visium-elf, applied on the mainline and 8 branch.
2019-02-15 Eric Botcaz
It cannot pass in PIE mode.
Tested on SPARC64/Linux, applied on all active branches.
2019-02-15 Eric Botcazou
* gcc.target/sparc/struct-ret-check-1.c: Add -fno-pie option.
--
Eric Botcazou
Index: gcc.target/sparc/struct-ret-check-1.c
On 8/16/18 12:18 PM, Martin Liška wrote:
> Hi.
>
> I'm going to install one more patch.
>
> Martin
>
Hi.
I'm going to install another 2 patches.
Thanks,
Martin
>From 37023f6a8e122d325cf3e3a054511425550cb6d6 Mon Sep 17 00:00:00 2001
From: marxin
Date: Fri, 15 Feb 2019 11:00:42 +0100
Subject:
Hi Christoph,
>
> On Thu, 14 Feb 2019 at 19:27, Tamar Christina
> wrote:
> >
> > Hi All,
> >
> > This patch fixes a failing testcase due to a use of dg-options instead
> > of dg-additional-options.
> >
> Makes sense.
> It doesn't fail in any of the configurations I test though, in what case do
On 2/14/19 10:13 PM, Steve Ellcey wrote:
> On Wed, 2019-02-13 at 12:34 +0100, Martin Liška wrote:
>> May I please ping this so that we can reach mainline soon?
>>
>> Thanks,
>> Martin
>
> Martin, I can't approve this patch but I can say that I have used it on
> Aarch64 and created a follow up patc
Hi Vlad,
On 13/02/2019 16:46, Vladimir Makarov wrote:
On 2019-02-13 5:54 a.m., Andre Vieira (lists) wrote:
PING.
Since Jeff is away can another maintainer have a look at this please?
I see the following patch
Yeah I uploaded the wrong patch... sorry. See attached, including a
testcase,
Hi.
The patch comes up with new summaries that use vector as underlying
data structure. In order to make the code more readable I decided to
factor out some common code into base classes.
Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
I tested building Inkscape w/ LTO and
Ping please, the issue is now PR 89302.
Thanks,
Martin
On Fri, Feb 01 2019, Martin Jambor wrote:
> Hi,
>
> even after the two previous HSA fixes, there is still one remining
> libgomp failure in the testsuite when run on an HSA-enabled APU. The
> problem is that grid calculation does not work w
Ping.
https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00345.html
Thanks,
Kyrill
On 2/6/19 1:52 PM, Kyrill Tkachov wrote:
[resending with patch compressed]
Hi all,
We're somewhat inconsistent in arm_neon.h when it comes to using the
implementation namespace for local
identifiers. This means
Andreas Schwab writes:
> This breaks non-split-stack builds.
>
> ../../../libgo/runtime/stack.c: In function 'doscanstack1':
> ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of
> 'scanstackblock' makes integer from pointer without a cast
> [-Werror=int-conversion]
> 113 | sc
On Thu, Feb 14, 2019 at 1:33 PM H.J. Lu wrote:
>
> Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
> by default with TARGET_MMX_WITH_SSE.
>
> For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> mode since MMX intrinsics can be emulated wit SSE.
>
> gcc
On 2/14/19 10:19 PM, Martin Sebor wrote:
> On 2/13/19 6:48 AM, Martin Liška wrote:
>> Hi.
>>
>> I'm sending patch where I document changes I made during GCC 9
>> development. I would appreciate both language and factical comments
>> about the patch.
>
> Nothing technical, just a few very minor lan
Updated version where I fixed one function comment.
Martin
>From fb1cf6f220d6af2c1676e58bd36b160fa8d9706b Mon Sep 17 00:00:00 2001
From: marxin
Date: Mon, 11 Feb 2019 14:58:31 +0100
Subject: [PATCH] Come up with fast {function,call}_summary classes (PR
ipa/89306).
gcc/ChangeLog:
2019-02-13 Ma
Hi Christoph,
>
> Looking at the logs, I see strange command lines when trying to compile
> arm_neon_softfp_fp16_ok:
> /aci-gcc-fsf/builds/gcc-fsf-gccsrc/obj-arm-none-linux-gnueabi/gcc3/gcc/xgcc
> -B/aci-gcc-fsf/builds/gcc-fsf-gccsrc/obj-arm-none-linux-gnueabi/gcc3/gcc/
> -fno-diagnostics-show-ca
On 2/14/19 11:37 PM, David Malcolm wrote:
> On Thu, 2019-02-14 at 14:19 -0700, Martin Sebor wrote:
>> On 2/13/19 6:48 AM, Martin Liška wrote:
>>> Hi.
>>>
>>> I'm sending patch where I document changes I made during GCC 9
>>> development. I would appreciate both language and factical comments
>>> ab
On Fri, Feb 15, 2019 at 12:15 AM Andreas Schwab wrote:
>
> This breaks non-split-stack builds.
>
> ../../../libgo/runtime/stack.c: In function 'doscanstack1':
> ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of
> 'scanstackblock' makes integer from pointer without a cast
> [-We
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
source operand is allowed.
2019-02-08 H.J. Lu
Uros Bizjak
PR target/89021
* config/i386/i386-protos.h (ix86_move_vec
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c (i
True if the operand is a register or an nonimmediate operand when
TARGET_MMX_WITH_SSE is false.
PR target/89021
* config/i386/predicates.md (mmx_nonimmediate_operand): New.
---
gcc/config/i386/predicates.md | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gcc/config/i386
On x86-64, since __m64 is returned and passed in XMM registers, we can
emulate MMX intrinsics with SSE instructions. To support it, we added
#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
;; Define instruction set of MMX instructions
(define_attr "mmx_isa" "base,native,x64,x64_noavx,x
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 21 +--
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
prototype.
* config/i386/i38
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
---
gcc/config/i386/mmx.md | 26 +++---
1 file
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
---
gcc/c
Emulate MMX ashr3/3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr3): Also allow
TARGET_MMX_WITH_SSE. Add SSE emulation.
(mmx_3): Likewise.
(ashr3): New.
(3): Likewise.
---
gcc/config/i386/mmx
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_3): Likewise.
Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 del
Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt3): Likewise.
---
Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.
PR target/89021
* config/i386/constraints.md (Yw): New constraint.
* config/i386/mmx.md (*vec_
Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_pinsrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 33 ++
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split a
Emulate MMX movntq with SSE2 movntidi. Only register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (sse_movntq): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386/mmx
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
PR target/89021
* config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation.
(sse_cvttps2pi): Likewise.
---
gcc/config/i386/sse.md | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (sse_cvtpi2ps): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. Add
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/con
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i3
PR target/89021
* config/i386/i386.c (ix86_expand_vector_init_duplicate): Set
mmx_ok to true if TARGET_MMX_WITH_SSE is true.
(ix86_expand_vector_init_one_nonzero): Likewise.
(ix86_expand_vector_init_one_var): Likewise.
(ix86_expand_vector_init_general
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_v8qi3): Likewise.
(smaxmin:v4hi3): New.
(umaxmin:v8qi3
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/xmmintrin.h: Em
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
define_insn_an
From: Uros Bizjak
2019-02-14 Uroš Bizjak
PR target/89021
* config/i386/i386.md (*zero_extendsidi2): Add mmx_isa attribute.
* config/i386/sse.md (*vec_concatv2sf_sse4_1): Ditto.
(*vec_concatv2sf_sse): Ditto.
(*vec_concatv2si_sse4_1): Ditto.
(*vec
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/mmx.
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
---
gcc/config/i38
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
gcc/config/i386/sse.md | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --gi
Emulate MMX abs2 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/sse.md (abs2): Add SSE emulation.
---
gcc/config/i386/sse.md | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/conf
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(*mmx_uavgv8qi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 21 +
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 22 ++---
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
* config/i386/i386-builtin.
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_uavgv4hi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 22 +
With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
when MMX is disabled.
PR target/89021
* config/i386/mmx.md (EMMS): Also allow TARGET_MMX_WITH_SSE.
(mmx_): Generate "" only when MMX is enabled.
---
gcc/config/i386/mmx.md | 6 --
1 file changed,
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Changed to
define_insn_and_split. Also allow TARGET_MMX_WITH_SSE. A
PR target/89021
* config/i386/mmx.md (MMXMODE:mov): Also allow
TARGET_MMX_WITH_SSE.
(MMXMODE:*mov_internal): Likewise.
(MMXMODE:movmisalign): Likewise.
---
gcc/config/i386/mmx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/c
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
gcc/config/i3
Emulate MMX 3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:3): New.
(any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
---
gcc/config/i386/mmx.md | 27 ---
1 file c
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Hi,
Martin discovered that inliner was adding deleted call graph edges to
its heap when supposedly processing newly discovered direct edges. The
problem is that a new edge created in the speculation part of the
indirect inlining machinery created speculative edges that were
immediately afterwards
On Fri, Feb 15, 2019 at 4:03 AM Rainer Orth
wrote:
>
> Andreas Schwab writes:
>
> > This breaks non-split-stack builds.
> >
> > ../../../libgo/runtime/stack.c: In function 'doscanstack1':
> > ../../../libgo/runtime/stack.c:113:18: error: passing argument 1 of
> > 'scanstackblock' makes integer f
This patch by Robin Dapp adds S/390 support to the internal/cpu
package. This partially addresses PR 89123. I bootstrapped it on
x86_64-pc-linux-gnu, which means little. Committed to mainline.
Ian
Index: gcc/go/gofrontend/MERGE
===
Dear Paul,
I've started putting together my observations on the current status of the
F2018 C interop extensions in gfortran 9.0. See the PRs
89363, 89364, 89365, 89366:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89363
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89364
https://gcc.gnu.org/bug
On Fri, Feb 15, 2019 at 6:03 AM H.J. Lu wrote:
>
> Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
> allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
> ---
> gcc/config/i386/mmx.md | 16 +---
> 1 file changed, 9
Status
==
The GCC 8 branch is now frozen for blocking regressions and documentation
fixes only, all changes to the branch require a RM approval now.
Quality Data
Priority # Change from last report
--- ---
P10
P2
On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote:
>
> True if the operand is a register or an nonimmediate operand when
> TARGET_MMX_WITH_SSE is false.
>
> PR target/89021
> * config/i386/predicates.md (mmx_nonimmediate_operand): New.
> ---
> gcc/config/i386/predicates.md | 7 +++
On 19/01/2019 23:37, Gerald Pfeifer wrote:
> On Thu, 10 Jan 2019, Sam Tebbs wrote:
>>> I believe this should also be covered in the GCC 9 release notes
>>> at https://gcc.gnu.org/gcc-9/changes.html ?
>> Sorry for the late reply. My email filters seem to have stumbled a bit
>> so I didn't pick this
On 2/14/19, David Malcolm wrote:
> On Thu, 2019-02-14 at 14:19 -0700, Martin Sebor wrote:
>> On 2/13/19 6:48 AM, Martin Liška wrote:
>> > Hi.
>> >
>> > I'm sending patch where I document changes I made during GCC 9
>> > development. I would appreciate both language and factical comments
>> > about
Hi All,
There's a bit of a disconnect between the feature flags that don't test the fpu
and ones that do when the test itself also forces an architecture. The forcing
of the architecture would change the defaults and without explicitly giving the
correct fpu again the test would fail.
I don't se
On Fri, Feb 15, 2019 at 3:03 PM H.J. Lu wrote:
>
> With SSE emulation of MMX intrinsics, we should make _mm_empty () as NOP
> when MMX is disabled.
>
> PR target/89021
> * config/i386/mmx.md (EMMS): Also allow TARGET_MMX_WITH_SSE.
> (mmx_): Generate "" only when MMX is enab
On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote:
>
> On x86-64, since __m64 is returned and passed in XMM registers, we can
> emulate MMX intrinsics with SSE instructions. To support it, we added
>
> #define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
>
> ;; Define instruction set of MMX inst
Darwin defines its own TARGET_FPMATH_DEFAULT, which should be
accompanied by corresponding TARGET_FPMATH_DEFAULT_P. Patch adds
missing define.
While looking around, I also fixed various whitespace issues in the header.
BTW: The header file still defines TARGET_64BIT which is horribly out
of date
On Fri, Feb 15, 2019 at 9:50 AM Uros Bizjak wrote:
>
> On Fri, Feb 15, 2019 at 2:58 PM H.J. Lu wrote:
> >
> > On x86-64, since __m64 is returned and passed in XMM registers, we can
> > emulate MMX intrinsics with SSE instructions. To support it, we added
> >
> > #define TARGET_MMX_WITH_SSE (TARG
On Fri, Feb 15, 2019 at 7:20 PM H.J. Lu wrote:
> > I went through the code again, and looks OK in general, modulo
> > mmx_nonimmediate_operand issue and a couple of minor issues.
> >
> > Please substitute nonimmediate_operand predicate with
> > mmx_nonimmediate_operand in expanders and insn patter
On 15.02.19 15:52, Ian Lance Taylor wrote:
> This patch by Robin Dapp adds S/390 support to the internal/cpu
> package. This partially addresses PR 89123. I bootstrapped it on
> x86_64-pc-linux-gnu, which means little. Committed to mainline.
fails in the -m31 multilib variant with
libtool: com
Replace "(MODE == V1DImode)" with "(MODE) == V1DImode".
* config/i386/i386.h (VALID_MMX_REG_MODE): Correct the misplaced
')'.
---
gcc/ChangeLog | 5 +
gcc/config/i386/i386.h | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/Chan
The attached patch is the third in a series for the above PR.
This one fixes erroneous padding with garbage characters in some
declaration and initialization expressions.
The issue here was that expr->representation is set when either
Hollerith strings are used or a TRANSFER statement is involved.
This patch to the Go frontend by Than McIntosh tweaks the recipe for
generating writeBarrier loads to insure that the dereference expr is
marked as not requiring a nil check. This should fix gcc PR 89368.
Bootstrapped and ran Go testsuite on x86_64-pc-linux-gnu. Committed
to mainline.
Ian
Index:
On 2/15/19 12:24 AM, Eric Botcazou wrote:
The attached patch removes the assumption introduced earlier today
in my fix for bug 87996 that the valid_constant_size_p argument is
a constant expression. I couldn't come up with a C/C++ test case
where this isn't true but apparently it can happen in A
> > OK, revised patch attached. I have manually verified that it yields the
> > expected result for an array of long doubles on 64-bit SPARC.
> >
> >
> > 2019-02-12 Eric Botcazou
> >
> > * asan.c (asan_expand_mark_ifn): Take into account the alignment of
> > the object to pick the si
Hi,
The following (og8 branch) patch added support for
attaching/detaching from dereferenced struct members:
https://gcc.gnu.org/ml/gcc-patches/2019-01/msg01778.html
Unfortunately I made a mistake in the portion of that patch that
inserts new alloc and firstprivate_pointer nodes for the struct b
Ping: https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00857.html
Jason, since you approved the original patch, can you please also
review this one? Due to the Ada test breakage there seems to be
some anxiety about getting the problem corrected soon.
Thanks
Martin
On 2/11/19 6:13 PM, Martin Sebor
> I'm ready to commit the patch once it's approved, and have been since
> the day the problem was reported.
Maybe CCing whoever approved the previous patch would help?
--
Eric Botcazou
On 2/15/19 3:46 PM, Eric Botcazou wrote:
I'm ready to commit the patch once it's approved, and have been since
the day the problem was reported.
Maybe CCing whoever approved the previous patch would help?
I just pinged the patch a few minutes ago and CC'd Jason. Sorry
about any trouble this
This automatically passes -funwind-tables when ASAN is used on Linux, as done
for other architectures, and also adjusts the shadow offset in 64-bit mode.
Tested on SPARC64/Linux, applied on the mainline.
2019-02-15 Eric Botcazou
* config/sparc/linux.h (ASAN_CC1_SPEC): Define.
One of the tests in g++.dg/asan/asan_oob_test.cc uses unaligned memory
accesses and g++.dg/asan/function-argument-3.C assumes a specific kind of
calling conventions for vectors.
Tested on SPARC64/Linux, applied on the mainline.
2019-02-15 Eric Botcazou
* g++.dg/asan/asan_oob_test.c
This patch by Cherry Zhang changes the Go compiler and runtime to use
__builtin_dwarf_cfa for getcallersp. Currently, the compiler lowers
runtime.getcallersp to __builtin_frame_address(1). In the C side of
the runtime, getcallersp is defined as __builtin_frame_address(0).
They don't match. Furth
On Tue, Feb 05, 2019 at 01:47:57PM +0100, Martin Liška wrote:
>
> gcc/fortran/ChangeLog:
>
> 2019-01-24 Martin Liska
>
> * decl.c (gfc_match_gcc_builtin): Add support for filtering
> of builtin directive based on multilib ABI name.
>
> gcc/testsuite/ChangeLog:
>
> 2019-01-24 Ma
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_3): Likewise.
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386-c.c (ix86_target_macros_internal): Define
__MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE.
* config/i386/i386.c (i
On x86-64, since __m64 is returned and passed in XMM registers, we can
emulate MMX intrinsics with SSE instructions. To support it, we added
#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2)
;; Define instruction set of MMX instructions
(define_attr "mmx_isa" "base,native,x64,x64_noavx,x
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
prototype.
* config/i386/i38
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
source operand is allowed.
2019-02-08 H.J. Lu
Uros Bizjak
PR target/89021
* config/i386/i386-protos.h (ix86_move_vec
Emulate MMX ashr3/3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr3): Also allow
TARGET_MMX_WITH_SSE. Add SSE emulation.
(mmx_3): Likewise.
(ashr3): New.
(3): Likewise.
---
gcc/config/i386/mmx
Emulate MMX 3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:mmx_3): Also allow
TARGET_MMX_WITH_SSE.
(any_logic:3): New.
(any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
---
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 25 +++
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