On Thu, Feb 14, 2019 at 3:12 PM H.J. Lu wrote:
>
> On Thu, Feb 14, 2019 at 2:57 PM Uros Bizjak wrote:
> >
> > On Thu, Feb 14, 2019 at 10:02 PM H.J. Lu wrote:
> >
> > > > > > > gcc/
> > > > > > >
> > > > > > > PR target/89021
> > > > > > > * config/i386/i386-builtin.def: Enable MM
Hi!
The following testcase is miscompiled on i686-linux, because
make_extraction is asked to make an extraction of 33 bits from DImode MEM
at position 0 and happily returns ZERO_EXTRACT with SImode (even when SImode
can hold only 32 bits), the caller (make_field_assignment) then on this
testcase b
On Fri, Feb 15, 2019 at 12:14 AM H.J. Lu wrote:
> > > > > > > > gcc/
> > > > > > > >
> > > > > > > > PR target/89021
> > > > > > > > * config/i386/i386-builtin.def: Enable MMX intrinsics
> > > > > > > > with
> > > > > > > > SSE/SSE2/SSSE3.
> > > > > > > > * config
On Thu, Feb 14, 2019 at 3:21 PM Uros Bizjak wrote:
>
> On Fri, Feb 15, 2019 at 12:14 AM H.J. Lu wrote:
>
> > > > > > > > > gcc/
> > > > > > > > >
> > > > > > > > > PR target/89021
> > > > > > > > > * config/i386/i386-builtin.def: Enable MMX intrinsics
> > > > > > > > > with
> > >
No functional changes.
2019-02-15 Uroš Bizjak
* config/i386/i386.h (TARGET_SUBTARGET64_ISA_DEFAULT):
Enable MMX, SSE and SSE2 by default.
* config/i386/i386.c (ix86_option_override_internal): Do not
explicitly set MMX, SSE and SSE2 flags for TARGET_64BIT here.
Bootstrapped and
Hi!
I did the following patch for the GCC 8 changes.html (in the 8.3 section):
Index: htdocs/gcc-8/changes.html
===
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-8/changes.html,v
retrieving revision 1.98
diff -u -r1.98 changes.html
--- htdoc
On Wed, Feb 13, 2019 at 5:21 PM Ian Lance Taylor wrote:
>
> Nikhil Benesch noticed that changes in the GCC backend were making the
> use of defer functions that call recover less efficient. A defer
> thunk is a generated function that looks like this (this is the entire
> function body):
>
>
This patch to the libgo gotest script runs examples when appropriate
in the libgo testsuite. An example with a "// Output:" comment is
supposed to be run, comparing the output of the example with the text
in the comment. Up until now we were not actually doing that, so we
were in effect skipping
On Thu, 14 Feb 2019, Jakub Jelinek wrote:
> Hi!
>
> We ICE on the following testcase, because while we save optimize,
> and optimize_{size,debug} vars during option saving/restoring, we don't save
> optimize_fast, and because of that end up with optimize 0 optimize_fast 1
> which the option handl
On Fri, 15 Feb 2019, Jakub Jelinek wrote:
> Hi!
>
> We ICE on the following testcase, because C nested functions are turned into
> !TREE_PUBLIC ones very soon, and the IPA code asserts that DECL_WEAK
> functions
> are either TREE_PUBLIC or DECL_EXTERNAL.
> As we reject static __attribute__((wea
This patch to the Go frontend and libgo by Nikhil Benesch harmonizes
types referenced by both C and Go. Compiling with LTO revealed a
number of cases in the runtime and standard library where C and Go
disagreed about the type of an object or function (or where Go and
code generated by the compiler
On Feb 13, 2019, at 1:09 AM, Jakub Jelinek wrote:
>
> ok for trunk?
Ok.
On Feb 13, 2019, at 5:37 AM, Jakub Jelinek wrote:
> Here is an updated patch that documents it. Bootstrapped/regtested on
> x86_64-linux and i686-linux, ok for trunk?
Ok.
On Feb 14, 2019, at 6:15 AM, Jakub Jelinek wrote:
> Ah, yes, UNRESOLVED doesn't show up visible when running tests by hand,
> rather than doing test_summary. Here is an updated patch that adds the
> needed dg-skip-if directives. Ok for trunk?
Ok.
NOTE_INSN_DELETED_LABEL is used to mark what used to be a 'code_label',
but was not used for other purposes than taking its address and was
transformed to mark that no code jumps to it. NOTE_INSN_DELETED_LABEL
is generated only in 3 places:
1. When delete_insn sees an unused label which is an exp
On February 14, 2019 11:52:17 PM GMT+01:00, Jakub Jelinek
wrote:
>Hi!
>
>The following testcase ICEs, because we try to gimplify a complex
>expression
>that with -ftrapv wants to emit multiple bbs. Fixed by using
>rewrite_to_non_trapping_overflow. Bootstrapped/regtested on
>x86_64-linux
>and i6
> The attached patch removes the assumption introduced earlier today
> in my fix for bug 87996 that the valid_constant_size_p argument is
> a constant expression. I couldn't come up with a C/C++ test case
> where this isn't true but apparently it can happen in Ada which I
> inadvertently didn't bu
On Fri, Feb 15, 2019 at 6:52 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following testcase ICEs, because we try to gimplify a complex expression
> that with -ftrapv wants to emit multiple bbs. Fixed by using
> rewrite_to_non_trapping_overflow. Bootstrapped/regtested on x86_64-linux
So with what con
On Fri, Feb 15, 2019 at 03:25:33PM +0800, Bin.Cheng wrote:
> So with what condition we can safely rewrite trapping operations into
> non trapping one? Does the rewrite nullify -ftrapv which requires
> trap behavior?
For the particular expression? Yes, otherwise no.
-ftrapv should be either repl
On Fri, Feb 15, 2019 at 08:33:44AM +0100, Jakub Jelinek wrote:
> On Fri, Feb 15, 2019 at 03:25:33PM +0800, Bin.Cheng wrote:
> > So with what condition we can safely rewrite trapping operations into
> > non trapping one? Does the rewrite nullify -ftrapv which requires
> > trap behavior?
>
> For th
On Thu, Feb 14, 2019 at 12:03 AM H.J. Lu wrote:
> > > > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX
> > > > > ISA
> > > > > by default with TARGET_MMX_WITH_SSE.
> > > > >
> > > > > For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
> > > > > mode si
Steve Ellcey writes:
> Szabolcs pointed out that my SIMD ABI patches that implement the
> aarch64_vector_pcs attribute do not generate a warning or error
> when being mixed with functions that do not have the attribute because
> the 'affects_type_identity' field was false in the attribute table.
>
This DR was already resolved for GCC 7.1 by the implementation of DR
2192, but we didn't have an explicit test for the behaviour that 2735
guarantees.
* doc/xml/manual/intro.xml: Document LWG 2735 status.
* include/bits/std_abs.h: Add comment about LWG 2735.
* testsuite/26
On Wed, Feb 13, 2019 at 12:14 AM Jakub Jelinek wrote:
>
> Hi!
>
> fold_binary_loc verifies that strlen argument is a pointer, but doesn't
> verify what the pointee is.
> The following patch just always converts it to the right pointer type
> (const char *) and dereferences only that.
> Another opt
On Wed, Feb 13, 2019 at 6:56 AM Martin Liška wrote:
>
> Hi.
>
> The patch is very similar to r236460 where we should release dominance info
> when the CFG is modified.
>
> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>
> Ready to be installed?
OK.
> Thanks,
> Martin
>
>
On Wed, Feb 13, 2019 at 7:59 AM Alan Modra wrote:
>
> Covers for a generic fortran bug. The effect is that we'll needlessly
> waste 64 bytes of stack space on some calls, but I don't see any
> simple and fully correct patch in generic code. Bootstrapped and
> regression tested powerpc64le-linux.
On Thu, Feb 14, 2019 at 12:08 AM Aaron Sawdey wrote:
>
> I've tracked pr/88308 down to move_insn_for_shrink_wrap(). This function
> moves an insn
> from one BB to another by copying it and deleting the old one. Unfortunately
> this does
> the LABEL_NUSES count on labels referenced because deleti
* testsuite/20_util/enable_shared_from_this/89303.cc: New test.
Tested x86_64-linux, committed to trunk.
commit 1a2917b994921926d37c609d386a2cc32ed65735
Author: Jonathan Wakely
Date: Thu Feb 14 09:16:04 2019 +
PR middle-end/89303 add testcase for std::enable_shared_from_this
On Thu, Feb 14, 2019 at 2:21 AM Ian Lance Taylor wrote:
>
> Nikhil Benesch noticed that changes in the GCC backend were making the
> use of defer functions that call recover less efficient. A defer
> thunk is a generated function that looks like this (this is the entire
> function body):
>
>
On Thu, Feb 14, 2019 at 9:16 AM Uros Bizjak wrote:
>
> On Thu, Feb 14, 2019 at 12:03 AM H.J. Lu wrote:
>
> > > > > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable
> > > > > > MMX ISA
> > > > > > by default with TARGET_MMX_WITH_SSE.
> > > > > >
> > > > > > For pr82483-1.c and p
Hi Iain,
> On Tue, 29 Jan 2019 at 13:24, Rainer Orth
> wrote:
>>
>> Solaris ld only gained support for section bracketing in Solaris 11.4.
>> Fortunately, in gdc it is only used for the minfo section, so it's easy
>> to provide a workaround by adding two additional startup files
>> drt{begin,end
On Thu, Feb 14, 2019 at 10:44 AM Richard Biener
wrote:
>
> On Thu, Feb 14, 2019 at 9:16 AM Uros Bizjak wrote:
> >
> > On Thu, Feb 14, 2019 at 12:03 AM H.J. Lu wrote:
> >
> > > > > > > Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable
> > > > > > > MMX ISA
> > > > > > > by default
Enabling of -fdec-include is missing from list of options enabled by
-fdec. When rendered as a PDF some lines are too long in the list of
options controlling Fortran dialect and in the list of options to
request or suppress errors and warnings.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=8934
> Hi.
>
> This is patch candidate I created and tested. It's not adding
> filtering based on opt_for_fn which I would defer to the next
> stage1.
>
> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>
> Ready to be installed?
> Thanks,
> Martin
> From d036f75a880bc91f67a54
On Wed, Feb 13, 2019 at 06:27:51PM -0800, H.J. Lu wrote:
> --- a/gcc/doc/options.texi
> +++ b/gcc/doc/options.texi
> @@ -227,7 +227,10 @@ options, their @code{Negative} properties should form a
> circular chain.
> For example, if options @option{-@var{a}}, @option{-@var{b}} and
> @option{-@var{c
Hi!
The following patch adds testcase coverage to make sure
-f{,no-}sanitize{,-recover}= options are all passed to the compiler backend
from the driver.
All these tests were broken by the earlier option handling patch from H.J.:
https://gcc.gnu.org/ml/gcc-patches/2019-02/msg00492.html
and as noth
On 11/20/18 11:58 AM, Martin Liška wrote:
> On 10/3/18 11:23 AM, Martin Liška wrote:
>> On 9/25/18 8:48 AM, Martin Liška wrote:
>>> Hi.
>>>
>>> One more tested patch.
>>>
>>> Martin
>>>
>>
>> One more tested patch.
>>
>> Martin
>>
>
> Hi.
>
> One another tested patch that I'm going to install.
>
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 21 +--
Emulate MMX 3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (any_logic:3): New.
(any_logic:*mmx_3): Also allow TARGET_MMX_WITH_SSE.
Add SSE support.
---
gcc/config/i386/mmx.md | 27 ---
1 file c
Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE.
PR target/89021
* config/i386/mmx.md (sse_cvtps2pi): Add SSE emulation.
(sse_cvttps2pi): Likewise.
---
gcc/config/i386/sse.md | 30 ++
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git
Emulate MMX packsswb/packssdw/packuswb with SSE packsswb/packssdw/packuswb
plus moving bits 64:95 to bits 32:63 in SSE register. Only SSE register
source operand is allowed.
2019-02-08 H.J. Lu
Uros Bizjak
PR target/89021
* config/i386/i386-protos.h (ix86_move_vec
Emulate MMX pshufw with SSE. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pshufw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(mmx_pshufw_1): Add SSE emulation.
(*vec_dupv4hi): Changed to define_insn_and_split a
PR target/89021
* config/i386/mmx.md (MMXMODE:mov): Also allow
TARGET_MMX_WITH_SSE.
(MMXMODE:*mov_internal): Likewise.
(MMXMODE:movmisalign): Likewise.
---
gcc/config/i386/mmx.md | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/c
Emulate MMX mmx_andnot3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (mmx_andnot3): Also allow
TARGET_MMX_WITH_SSE. Add SSE support.
---
gcc/config/i386/mmx.md | 18 +++---
1 file changed, 11 insertions(+), 7 del
Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_pinsrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 33 ++
Emulate MMX mmx_pextrw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pextrw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/mmx.
Emulate MMX plusminus/sat_plusminus with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (MMXMODEI8): Require TARGET_SSE2 for V1DI.
(plusminus:mmx_3): Check
TARGET_MMX_WITH_SSE.
(sat_plusminus:mmx_3): Likewise.
Emulate MMX version of pshufb with SSE version by masking out the bit 3
of the shuffle control byte. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pshufbv8qi3): Renamed to ...
(ssse3_pshufbv8qi3_mmx): This.
(ssse3_pshufbv8
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add
SSE support.
---
gcc/c
In 64-bit mode, SSE2 can be used to emulate MMX instructions without
3DNOW. We can use SSE2 to support MMX register modes.
PR target/89021
* config/i386/i386.c (ix86_set_reg_reg_cost): Add support for
TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE.
(ix86_vector_mode_s
Emulate MMX mmx_umulv4hi3_highpart with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_umulv4hi3_highpart): Also check
TARGET_MMX and TARGET_MMX_WITH_SSE.
(*mmx_umulv4hi3_highpart): Add SSE emulation.
---
gcc/config/i38
Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
destination XMM register. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (sse_cvtpi2ps): Renamed to ...
(*mmx_cvtpi2ps): This. Disabled for TARGET_MMX_WITH_SSE.
Emulate MMX mulv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mulv4hi3): New.
(*mmx_mulv4hi3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
---
gcc/config/i386/mmx.md | 26 +++---
1 file
Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX. For MMX punpckhXX,
move bits 64:127 to bits 0:63 in SSE register. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/i386-protos.h (ix86_split_mmx_punpck): New
prototype.
* config/i386/i38
Emulate MMX mmx_eq/mmx_gt3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_eq3): Also allow
TARGET_MMX_WITH_SSE.
(*mmx_eq3): Also allow TARGET_MMX_WITH_SSE. Add SSE
support.
(mmx_gt3): Likewise.
---
On x86-64, since __m64 is returned and passed in XMM registers, we can
emulate MMX intrinsics with SSE instructions. To support it, we added
#define TARGET_MMX_WITH_SSE \
(TARGET_64BIT && TARGET_SSE2 && !TARGET_3DNOW)
SSE emulation is disabled for 3DNOW since 3DNOW patterns haven't been
update
Emulate MMX movntq with SSE2 movntidi. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse_movntq): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/gcc/config/i386
Emulate MMX ashr3/3 with SSE. Only SSE register
source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_ashr3): Changed to define_expand.
Disallow TARGET_MMX_WITH_SSE.
(mmx_3): Likewise.
(ashr3): New.
(*ashr3): Likewise.
(3): Li
Emulate MMX vec_dupv2si with SSE. Add the "Yw" constraint to allow
broadcast from integer register for AVX512BW with TARGET_AVX512VL.
Only SSE register source operand is allowed.
PR target/89021
* config/i386/constraints.md (Yw): New constraint.
* config/i386/mmx.md (*vec_
Since we now emulate MMX intrinsics with SSE in 64-bit mode, we can
enable SSSE3 __m64 tests even when AVX is enabled.
PR target/89021
* gcc.target/i386/ssse3-pabsb.c: Also enable __m64 check in
64-bit mode.
* gcc.target/i386/ssse3-pabsd.c: Likewise.
* gcc.t
Emulate MMX mmx_uavgv4hi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv4hi3): Also check TARGET_MMX and
TARGET_MMX_WITH_SSE.
(*mmx_uavgv4hi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 22 +
Emulate MMX ssse3_pmulhrswv4hi3 with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/sse.md (*ssse3_pmulhrswv4hi3): Add SSE emulation.
---
gcc/config/i386/sse.md | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --gi
Emulate MMX mmx_psadbw with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_psadbw): Add SSE emulation.
---
gcc/config/i386/mmx.md | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i386/
Emulate MMX mmx_uavgv8qi3 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_uavgv8qi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(*mmx_uavgv8qi3): Add SSE emulation.
---
gcc/config/i386/mmx.md | 21 +
Emulate MMX abs2 with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/sse.md (abs2): Add SSE emulation.
---
gcc/config/i386/sse.md | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/conf
PR target/89021
* config/i386/i386.c (ix86_expand_vector_init_duplicate): Set
mmx_ok to true if TARGET_MMX_WITH_SSE is true.
(ix86_expand_vector_init_one_nonzero): Likewise.
(ix86_expand_vector_init_one_var): Likewise.
(ix86_expand_vector_init_general
Allow MMX intrinsic emulation with SSE/SSE2/SSSE3. Don't enable MMX ISA
by default with TARGET_MMX_WITH_SSE.
For pr82483-1.c and pr82483-2.c, "-mssse3 -mno-mmx" compiles in 64-bit
mode since MMX intrinsics can be emulated wit SSE.
gcc/
PR target/89021
* config/i386/i386-builtin.
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_v8qi3): Likewise.
(smaxmin:v4hi3): New.
(umaxmin:v8qi3
Emulate MMX version of palignrq with SSE version by concatenating 2
64-bit MMX operands into a single 128-bit SSE operand, followed by
SSE psrldq. Only SSE register source operand is allowed.
PR target/89021
* config/i386/sse.md (ssse3_palignrdi): Changed to
define_insn_an
Emulate MMX mmx_pmovmskb with SSE by zero-extending result of SSE pmovmskb
from QImode to SImode. Only SSE register source operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmovmskb): Changed to
define_insn_and_split to support SSE emulation.
---
gcc/config/i3
Emulate MMX ssse3_pmaddubsw with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_pmaddubsw): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/con
Emulate MMX ssse3_phwv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phwv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX ssse3_phdv2si3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_phdv2si3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.m
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/i386-c.c (ix86_
Emulate MMX umulv1siv1di3 with SSE2. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/mmx.md (sse2_umulv1siv1di3): Add SSE emulation
support.
(*sse2_umulv1siv1di3): Add SSE2 emulation.
---
gcc/config/i386/mmx.md | 22 ++---
Emulate MMX ssse3_psign3 with SSE. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_psign3): Add SSE emulation.
---
gcc/config/i386/sse.md | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/gcc/config/i3
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/
On Thu, Feb 14, 2019 at 10:32:50AM +0100, Richard Biener wrote:
> On Wed, Feb 13, 2019 at 7:59 AM Alan Modra wrote:
> >
> > Covers for a generic fortran bug. The effect is that we'll needlessly
> > waste 64 bytes of stack space on some calls, but I don't see any
> > simple and fully correct patch
Mark,
> Patch and change log attached to PR.
Could you please submit this the normal way, with the ChangeLog in the text and
the patch ad attachment?
Regards, Thomas
Enabling of -fdec-include is missing from list of options enabled by
-fdec. When rendered as a PDF some lines are too long in the list of
options controlling Fortran dialect and in the list of options to
request or suppress errors and warnings.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=8934
On Thu, Feb 14, 2019 at 3:09 AM Jakub Jelinek wrote:
>
> Hi!
>
> The following patch adds testcase coverage to make sure
> -f{,no-}sanitize{,-recover}= options are all passed to the compiler backend
> from the driver.
>
> All these tests were broken by the earlier option handling patch from H.J.:
On Thu, Feb 14, 2019 at 12:03:30PM +0100, Jakub Jelinek wrote:
> On Wed, Feb 13, 2019 at 06:27:51PM -0800, H.J. Lu wrote:
> > --- a/gcc/doc/options.texi
> > +++ b/gcc/doc/options.texi
> > @@ -227,7 +227,10 @@ options, their @code{Negative} properties should form
> > a circular chain.
> > For exam
Hi!
PR72715 "ICE in gfc_trans_omp_do, at fortran/trans-openmp.c:3164" is the
OpenACC variant of the OpenMP PR60127 "ICE with OpenMP and DO CONCURRENT"
(trunk r210331) changes.
On Mon, 29 Aug 2016 14:33:07 -0700, Cesar Philippidis
wrote:
> It looks like the fortran FE has some preliminary suppor
On 2/14/19 12:23 PM, Martin Liška wrote:
> On 11/20/18 11:58 AM, Martin Liška wrote:
>> On 10/3/18 11:23 AM, Martin Liška wrote:
>>> On 9/25/18 8:48 AM, Martin Liška wrote:
Hi.
One more tested patch.
Martin
>>>
>>> One more tested patch.
>>>
>>> Martin
>>>
>>
>> Hi.
>>
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX ashr3/3 with SSE. Only SSE register
> source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (mmx_ashr3): Changed to define_expand.
> Disallow TARGET_MMX_WITH_SSE.
> (mmx_3): Likewise.
>
Although there is no good use for stack> or similar
types with a mismatched value_type, it's possible somebody is doing that
and getting away with it currently. This patch only enforces the new
requirement for C++17 and later. During stage 1 we should consider
enforcing it for C++11 and C++14.
This change is safe to make now (in stage 4), because the constructors
are currently incorrect and unusable (unless the supplied container
already contains a heap, in which case the new make_heap calls are
redundant but harmless).
* doc/xml/manual/intro.xml: Document LWG 2537 status.
* configure.ac: Check for C11 timespec_get function.
* crossconfig.m4 (freebsd, linux, gnu, cygwin, solaris, netbsd)
(openbsd): Likewise
* config.h.in: Regenerate.
* configure: Regenerate.
* include/c_global/ctime (timespec, timespec_get): Add to nam
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX sse_cvtpi2ps with SSE2 cvtdq2ps, preserving upper 64 bits of
> destination XMM register. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/mmx.md (sse_cvtpi2ps): Renamed to ...
>
On Thu, Feb 14, 2019 at 05:48:29AM -0800, H.J. Lu wrote:
> I got
>
> UNRESOLVED: c-c++-common/ubsan/opts-1.c -O2 -flto
> -fuse-linker-plugin -fno-fat-lto-objects scan-tree-dump-times
> optimized "__ubsan_handle_divrem_overflow" 2
Ah, yes, UNRESOLVED doesn't show up visible when running tests
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX movntq with SSE2 movntidi. Only SSE register source operand
> is allowed.
There is no SSE register source operand. Probably "Only register
source operand is allowed."
Uros.
>
> PR target/89021
> * config/i386/mmx.md
On Thu, Feb 14, 2019 at 1:30 PM H.J. Lu wrote:
>
> Emulate MMX version of pshufb with SSE version by masking out the bit 3
> of the shuffle control byte. Only SSE register source operand is allowed.
>
> PR target/89021
> * config/i386/sse.md (ssse3_pshufbv8qi3): Renamed to ...
>
> "Marc" == Marc Glisse writes:
>> Lastly, in the case of uninitialized variables, the usual solution
>> of initializing them is trivial and always safe (some coding styles
>> even require it).
Marc> Here it shows that we don't work with the same type of code at all. If
Marc> I am using a bo
On 2/11/19 2:35 PM, Matthew Malcomson wrote:
On 10/02/19 09:42, Christophe Lyon wrote:
>
> Both this simple patch or the previous fix all the ICEs I reported,
thanks.
>
> Of course, the scan-assembler failures remain to be fixed.
>
In the testcase I failed to account for targets that don't s
When -mmanual-endbr is used with -fcf-protection, only functions marked
with cf_check attribute should be instrumented with ENDBR. We should
skip rest_of_insert_endbranch on functions without cf_check attribute.
OK for trunk?
Thanks.
H.J.
---
gcc/
PR target/89353
* config/i386/
Because uses-allocator construction is invariably done with a const
lvalue the __uses_alloc helper should use a const lvalue for the
is_constructible checks. Otherwise, it can detect that the type can be
constructed from an rvalue, and then an error happens when a const
lvalue is passed to the con
* doc/xml/manual/status_cxx2017.xml: Add P0063R3 to status table.
* doc/html/*: Regenerate.
Committed to trunk.
I've also updated the LibstdcxxTodo wiki page:
https://gcc.gnu.org/wiki/LibstdcxxTodo?action=diff&rev2=107&rev1=100
commit 5f7cebfc9de5a7c07c447d06b610002964065730
Au
Hi Jakub,
> The following testcase is miscompiled on x86_64-linux (-m32 and -m64) at
> -O1, as a pointer has two vars in points-to set, the first one is escaped
> heap var and the second one is escaped non-heap var, and in the end the last
> var that sets vars_contains_escaped won and overwrote
>
On 2/6/19 9:23 PM, David Malcolm wrote:
PR c++/88680 reports excess warnings from -Wtype-limits after the C++
FE's use of location wrappers was extended in r267272 for cases such as:
const unsigned n = 8;
static_assert (n >= 0 && n % 2 == 0, "");
t.C:3:18: warning: comparison of unsigned
On Thu, Feb 14, 2019 at 10:32:50AM +0100, Richard Biener wrote:
> On Wed, Feb 13, 2019 at 7:59 AM Alan Modra wrote:
> >
> > Covers for a generic fortran bug. The effect is that we'll needlessly
> > waste 64 bytes of stack space on some calls, but I don't see any
> > simple and fully correct patch
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