On Fri, May 13, 2016 at 5:53 PM, Richard Biener
wrote:
> On May 13, 2016 6:02:27 PM GMT+02:00, Bin Cheng wrote:
>>Hi,
>>As PR69848 reported, GCC vectorizer now generates comparison outside of
>>VEC_COND_EXPR for COND_REDUCTION case, as below:
>>
>> _20 = vect__1.6_8 != { 0, 0, 0, 0 };
>> vect_c
> The following patch adds BIT_FIELD_INSERT, an operation to
> facilitate doing bitfield inserts on registers (as opposed
> to currently where we'd have a BIT_FIELD_REF store).
Why not call it BIT_FIELD_INSERT_EXPR instead to make it clear that it's an
expression and not a mere operation?
> Orig
Hi,
-fstack-usage issues the "not supported by this target" warning on naked
functions because the prologue routines do an early return for them.
Tested on arm-eabi, may I apply it on all active branches?
2016-05-16 Eric Botcazou
* config/arm/arm.c (arm_expand_prologue): Set the st
This brings consistency to the way host tools are invoked when doing canadian
cross builds with Ada: gnattools was using host_alias and gcc/ada host, while
the most correct incantation is probably host_noncanonical.
Tested on x86_64-suse-linux, applied on the mainline.
2016-05-16 Eric Botcazo
The support of vfma_n_f64, vfms_n_f32, vfmsq_n_f32, vfmsq_n_f64 are
missing in current gcc arm_neon.h.
Meanwhile, besides "(fma (vec_dup (vec_select)))", fma by element can
also comes from "(fma (vec_dup(scalar" where the scalar value is already
sitting in vector register then duplicated to other
AArch64 support vector multiply by element for V2DF, V2SF, V4SF, V2SI,
V4SI, V4HI, V8HI.
All above are well supported by "*aarch64_mul3_elt" pattern and
"*aarch64_mul3_elt_" if there is lane size
change.
Above patterns are trying to match "(mul (vec_dup (vec_select)))"
which is genuinely vector
This patch reimplement vector multiply by element on top of the existed
vmul_lane* intrinsics instead of inline assembly.
There is no code generation change from this patch.
OK for trunk?
2016-05-16 Jiong Wang
gcc/
* config/aarch64/aarch64-simd.md (vmul_n_f32): Remove inline assembly.
Use
This patch remove inline assembly and reimplement all mvn/mvnq vector
integer intrinsics through the standard "one_cmpl2" pattern was
introduced later after the initial implementation of those intrinsics.
that's why inline assembly was used historically.
OK for trunk?
no regression on the exist
Robert Suchanek writes:
> A small patch to correct the latency for M5100.
>
> Ok to commit?
> * config/mips/m5100.md (m51_int_load): Update the latency to 2.
OK.
Matthew
On 05/16/2016 12:22 AM, Jan Hubicka wrote:
> Hi,
> this patch teach inliner to inline into thunks. This is easy to do - all we
> need
> is to produce a gimple body when we decide to do so. This fixes some ages old
> xfails
> and enables some 40k inlines in Firefox. Not all those inlines are win,
Robert Suchanek
> The below enables LSA/DLSA instructions for -mmsa.
>
> Ok to commit?
OK.
There is a corresponding testsuite change needed for this
as some code quality tests change if LSA is available. This
is the HAS_LSA 'ghost' option in mips.exp. I'm happy to leave
this to be dealt with
Hi,
this patch fixes ICE when thunk is inlined and call within thunk too. We need
to recurse in this case because inlining thunk does not introduce a new basic
blocks
like normal inlining does.
Bootstrapped/regtested x86_64-linux, comitted.
Honza
Index: ChangeLog
===
On Mon, Apr 25, 2016 at 10:42 AM, marxin wrote:
> gcc/ChangeLog:
>
> 2016-04-25 Martin Liska
>
> * tree-ssa-loop-ivopts.c(comp_cost::operator=): New function.
> (comp_cost::infinite_cost_p): Likewise.
> (operator+): Likewise.
> (comp_cost::operator+=): Likewise.
This change ensures that the packing of array types subject to pragma Pack
and whose component type is a record with a size in the range 33 .. 63 bits
is optimal, in the sense that the 'Component_Size is equal to the 'Size of
the component type.
The following package P must yield the specified out
> On 05/16/2016 12:22 AM, Jan Hubicka wrote:
> > Hi,
> > this patch teach inliner to inline into thunks. This is easy to do - all we
> > need
> > is to produce a gimple body when we decide to do so. This fixes some ages
> > old xfails
> > and enables some 40k inlines in Firefox. Not all those inl
ping
From: Wilco Dijkstra
Sent: 27 April 2016 17:39
To: James Greenhalgh
Cc: gcc-patches@gcc.gnu.org; nd
Subject: Re: [PATCH][AArch64] print_operand should not fallthrough from
register operand into generic operand
James Greenhalgh wrote:
> So the part of
ping
From: Wilco Dijkstra
Sent: 22 April 2016 17:15
To: gcc-patches@gcc.gnu.org
Cc: nd
Subject: [PATCH][AArch64] Improve aarch64_case_values_threshold setting
GCC expands switch statements in a very simplistic way and tries to use a table
expansion even wh
Hi,
This is an obvious patch documenting vect_cond_mixed in sourcebuild.texi. OK?
Thanks,
bin
2016-05-13 bin cheng
* doc/sourcebuild.texi (@item vect_cond_mixed): New item.diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 3142cd5..f1bd9be 100644
--- a/gcc/doc/sou
This patch cleans up the implementation of packed array types, which is shared
between the front-end proper and gigi (because the middle-end doesn't support
bit packing for array types, unlike for record types through bit fields).
The two main changes are the reduced usage of bit packing (not nece
This plugs a small loophole in the implementation of pragma Implicit_Packing
for array types, when the component type is scalar and has a size multiple of
the storage unit but not a power of 2.
The following package must compile quietly:
pragma Implicit_Packing;
package P is
type Int24 is mod
The implementation of pragma Implicit_Packing for record types was restricted
to scalar components, i.e. it gave up as soon as there was one non-scalar
component in the record type. This change extends it to all the other kinds
of components, at least if they are small.
The following package must
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'cpplib' has been submitted
by the Danish team of translators. The file is available at:
http://translationproject.org/latest/cpplib/da.po
(This file, 'cpplib-6.1.0.da.po',
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On Wed, Apr 27, 2016 at 05:39:33PM +0100, Wilco Dijkstra wrote:
> James Greenhalgh wrote:
> > So the part of this patch removing the fallthrough to general operand
> > is not OK for trunk.
> >
> > The other parts look reasonable to me, please resubmit just those.
>
> Right, I removed the removal o
On Mon, May 16, 2016 at 11:38:04AM +0100, Wilco Dijkstra wrote:
> ping
As this change will change code generation for all cores (except
Exynos-M1), I'd like to hear from those with more detailed knowledge of
ThunderX, X-Gene and qdf24xx before I take this patch.
Let's give it another week or so f
The transformation is either useless or counter-productive or even wrong.
Tested on x86_64-suse-linux, applied on the mainline.
2016-05-16 Eric Botcazou
* gcc-interface/decl.c (gnat_to_gnu_entity) : Do not
build a specific type for the object if it is deemed a constant.
--
Hello, gentle maintainer.
This is a message from the Translation Project robot.
A revised PO file for textual domain 'gcc' has been submitted
by the Danish team of translators. The file is available at:
http://translationproject.org/latest/gcc/da.po
(This file, 'gcc-6.1.0.da.po', has just
Sorry, that was the wrong vector-6.c — should have realized. In any case, for
each of the vector tests, we get appropriate use of element-wise loads, and no
load-hit-store bitfield assignments, so the code generation is what we want to
see. Sorry for the misleading information.
Bill
> On May
Maciej Rozycki writes:
> On Wed, 4 May 2016, Matthew Fortune wrote:
>
> > diff --git a/gcc/config/mips/mips-cpus.def
> > b/gcc/config/mips/mips-cpus.def index 17034f2..5df9807 100644
> > --- a/gcc/config/mips/mips-cpus.def
> > +++ b/gcc/config/mips/mips-cpus.def
> > @@ -44,10 +44,7 @@ MIPS_CPU ("
On 05/13/16 12:39, Alexander Monakov wrote:
This regresses offloading compilation: the new hook isn't applied during LTO
stream-in, so target functions named 'call' won't be remapped.
foop :( I've restored the old behaviour.
nathan
On 11/05/16 16:46, Joseph Myers wrote:
On Wed, 11 May 2016, Tejas Belagod wrote:
AFAICS, I don't think it mandates a double-rounding behavior for double to
__fp16 conversions and I don't see a change in stand between the two versions
of ACLE on the behavior of __fp16.
It's not a change betwee
On 11/05/16 14:23, Christophe Lyon wrote:
2016-05-02 Christophe Lyon
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Fix typo in
comment.
Ok (I agree it's obvious)
Thanks,
Kyrill
Change-Id: I7244c0dc0a5ab2dbcec65b40c050f72f92707139
diff --git a/gcc/testsuite/gcc.target
On 11/05/16 14:23, Christophe Lyon wrote:
2016-05-02 Christophe Lyon
* gcc.target/aarch64/advsimd-intrinsics/vmul.c: Remove useless #ifdef.
* gcc.target/aarch64/advsimd-intrinsics/vshl.c: Likewise.
* gcc.target/aarch64/advsimd-intrinsics/vtst.c: Likewise.
Ok.
Thanks
On 11/05/16 14:23, Christophe Lyon wrote:
It is useful to have more detailed information in the logs when checking
validation results: instead of repeating the intrinsic name, we now print
its return type too.
Ok.
Thanks,
Kyrill
2016-05-02 Christophe Lyon
* gcc.target/aarch64/adv
On 13/05/16 15:22, Christophe Lyon wrote:
On 13 May 2016 at 16:08, James Greenhalgh wrote:
On Wed, May 11, 2016 at 03:23:54PM +0200, Christophe Lyon wrote:
2016-05-02 Christophe Lyon
* gcc.target/aarch64/advsimd-intrinsics/vsli_n.c: Add check for
vsliq_n_u64.
And vsliq_n_s64 ?
On 11/05/16 14:23, Christophe Lyon wrote:
2016-05-02 Christophe Lyon
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Add
missing tests for vreinterpretq_p{8,16}.
Ok.
Thanks,
Kyrill
Change-Id: I7e9bb18c668c34685f12aa578868d7752232a96c
diff --git a/gcc/testsuite/gc
James Greenhalgh wrote:
> As this change will change code generation for all cores (except
> Exynos-M1), I'd like to hear from those with more detailed knowledge of
> ThunderX, X-Gene and qdf24xx before I take this patch.
>
> Let's give it another week or so for comments, and expand the CC list.
N
On 11/05/16 14:23, Christophe Lyon wrote:
2016-05-02 Christophe Lyon
* gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add fp16 tests.
I thought for a bit wrapping the expected_f16, expectedq_f16 and other
declarations
in an "#if defined (__ARM_FP16_FORMAT_IEEE) || defined
(__
Hello.
Sending the rebased version of the patch.
Martin
>From a91b1578f3907e05543b2acea0081b6e4744ade9 Mon Sep 17 00:00:00 2001
From: marxin
Date: Mon, 16 May 2016 15:52:56 +0200
Subject: [PATCH 2/2] Add profiling support for IVOPTS
gcc/ChangeLog:
2016-04-25 Martin Liska
* tree-ssa-loop-i
On 05/16/2016 12:13 PM, Bin.Cheng wrote:
> Hi Martin,
> Could you please rebase this patch and the profiling one against
> latest trunk? The third patch was applied before these two now.
>
> Thanks,
> bin
Hello.
Sending the rebased version of the patch.
Martin
>From a91b1578f3907e05543b2acea00
Hi Guys,
Currently dwarf2out.c:mem_loc_descriptor() has some special case
code to handle the situation where an address is held in a register
whose mode is not of type MODE_INT. It generates a
DW_OP_GNU_regval_type expression which may later on be converted into
a frame pointer based ex
Hi,
the patch below fixes PR 70857. When the HSA gridification code
copies the declaration of the function for outlining the target
construct, it left the old RESULT_DECL dangling to it. I did not
notice because it has VOID_TYPE but it needs to be done nevertheless,
not least because ipa-pta cho
> > Ok to commit?
>
> > * config/mips/m5100.md (m51_int_load): Update the latency to 2.
>
> OK.
Committed - r236288
Robert
On Mon, May 16, 2016 at 04:25:10PM +0200, Martin Jambor wrote:
> the patch below fixes PR 70857. When the HSA gridification code
> copies the declaration of the function for outlining the target
> construct, it left the old RESULT_DECL dangling to it. I did not
> notice because it has VOID_TYPE b
Hi Matthew,
> > Ok to commit?
>
> OK.
Done as r236289.
> There is a corresponding testsuite change needed for this
> as some code quality tests change if LSA is available. This
> is the HAS_LSA 'ghost' option in mips.exp. I'm happy to leave
> this to be dealt with as part of the overall MSA t
On 05/16/2016 05:01 AM, Bin Cheng wrote:
Hi,
This is an obvious patch documenting vect_cond_mixed in sourcebuild.texi. OK?
Thanks,
bin
2016-05-13 bin cheng
* doc/sourcebuild.texi (@item vect_cond_mixed): New item.
Assuming the information is technically correct, the patch looks O
Hi all,
The gcc.target/aarch64/cpu-diagnostics* tests specify invalid -mcpu options and
look for the expected error.
However, if the user overrides the -mcpu option when testing the tests start
FAILing because they don't get
the expected bad -mcpu option.
This patch skips those tests when that
Hi!
This patch tweaks various spots, including being able to compile taskloop
construct. I'll be adding more testcases and tweaking the code further
later on.
2016-05-16 Jakub Jelinek
* trans.c (trans_code): Handle new OpenMP 4.5 constructs.
* resolve.c (gfc_resolve_blocks):
This patch set adds a BRIG (HSAIL) frontend. It can be used as a core
for an HSAIL finalizer implementation for processors with gcc backends.
It is a bit unusual frontend as the consumed format is a binary
representation. The textual HSAIL can be compiled to it with a
separate assembler.
The fr
The configuration file changes and misc. updates required
by the BRIG frontend.
Also, added include/hsa-interface.h which is hsa.h taken from libgomp
and will be shared by it (agreed with Martin Liška / SUSE).
--
Pekka Jääskeläinen
Parmance
The configuration file changes and misc. updates requir
The BRIG frontend itself.
--
Pekka Jääskeläinen
Parmance
002-brig-fe-new-files.patch.gz
Description: application/gzip
A smoke test suite. The patch has been tested more thoroughly with the
proprietary HSA PRM conformance suite.
Requires the HSAILasm tool to first compile the .hsail to .brig.
--
Pekka Jääskeläinen
Parmance
A smoke test suite. The patch has been tested more thoroughly with the
proprietary HSA PRM
While debugging PR71146 I notices these. These typos are perfidious because
they make grepping for '__builtin_unreachable' harder.
Applying to trunk as obvious.
2016-05-16 Marek Polacek
* gimple.c (maybe_remove_unused_call_args): Fix typos in the
commentary.
diff --git gcc/g
Hi,
in the last round fo alignment fixes, we have forgot to make sure that
all symbols are at least naturally aligned, which is a hard HSAIL
requirement. This caused problems when emitting a symbol for a
private complex number, as the natural alignment as defined by HSAIL
is twice the one of the
On Fri, May 13, 2016 at 08:23:16PM -0500, Segher Boessenkool wrote:
> On Fri, May 13, 2016 at 07:25:43PM -0400, Michael Meissner wrote:
> > This patch adds support for the 32-bit word splat instructions, the byte
> > immediate splat instructions, and the vector sign extend instructions to GCC
> > 7
On 05/06/2016 09:19 AM, Jakub Jelinek wrote:
On Fri, May 06, 2016 at 11:11:29PM +0800, Marcel Böhme wrote:
+ dpi.copy_templates
+= (struct d_print_template *) malloc (((size_t) dpi.num_copy_templates)
+ * sizeof (*dpi.copy_templates));
+ if (! dpi.co
On Mon, May 16, 2016 at 12:12:38PM -0600, Jeff Law wrote:
> On 05/06/2016 09:19 AM, Jakub Jelinek wrote:
> >On Fri, May 06, 2016 at 11:11:29PM +0800, Marcel Böhme wrote:
> >>+ dpi.copy_templates
> >>+= (struct d_print_template *) malloc (((size_t) dpi.num_copy_templates)
> >>+
On 05/16/2016 12:19 PM, Jakub Jelinek wrote:
On Mon, May 16, 2016 at 12:12:38PM -0600, Jeff Law wrote:
On 05/06/2016 09:19 AM, Jakub Jelinek wrote:
On Fri, May 06, 2016 at 11:11:29PM +0800, Marcel Böhme wrote:
+ dpi.copy_templates
+= (struct d_print_template *) malloc (((size_t) dpi.num_c
On 05/13/2016 12:50 PM, Marc Glisse wrote:
Hello,
when VRP does some transforms, it may create new SSA_NAMEs, but doesn't
give them range information. This can prevent cascading transformations
in a single VRP pass. With this patch, I assign range information to the
variable introduced by one tr
On 05/12/2016 08:29 AM, David Malcolm wrote:
One wart I ran into is that system.h has this:
/* Front ends should never have to include middle-end headers. Enforce
this by poisoning the header double-include protection defines. */
#ifdef IN_GCC_FRONTEND
#pragma GCC poison GCC_RTL_H GCC_EXCE
On 05/11/2016 09:46 AM, Martin Jambor wrote:
Hi,
when analyzing PR 70646, I found out that --param ipa-max-agg-items=0
does not prevent creation of aggregate jump functions because it is
checked only after the first such jump function is created. The
following patch fixes that by checking the p
2016-05-16 Uros Bizjak
* config/i386/xopintrin.h: Correct "unsinged" typo in the comments.
Committed as obvious.
Uros.
Index: config/i386/xopintrin.h
===
--- config/i386/xopintrin.h (revision 236296)
+++ config/i386/xopin
On 04/29/2016 03:35 AM, Dominik Vogt wrote:
On Wed, Apr 27, 2016 at 10:24:21PM -0600, Jeff Law wrote:
Instead you want insn 12 to use a zero-extend to extend (reg:SI 64)
into (reg:DI 2)?
Yes, because we get the zero extend for free in this case (through
the constant in the AND or because the i
On 05/11/2016 02:52 AM, Dominik Vogt wrote:
On Wed, May 11, 2016 at 10:40:11AM +0200, Bernd Schmidt wrote:
On 05/11/2016 09:42 AM, Dominik Vogt wrote:
On Tue, May 10, 2016 at 05:05:06PM +0200, Bernd Schmidt wrote:
Earlier in the discussion you mentioned the intention to remove
these costs. Not
On 05/12/2016 10:08 AM, Martin Jambor wrote:
Hi,
this patch simply makes parm_preserved_before_stmt_p consider all
const PARM_DECLs constant and does not invoke AA walking on them
(really the DECLs themselves, not the memory they might point to).
Bootstrapped and lto-bootstrapped and tested on
Ping 2 of the following patch:
https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00013.html
On 05/09/2016 10:38 AM, Martin Sebor wrote:
Pinging the following patch:
https://gcc.gnu.org/ml/gcc-patches/2016-05/msg00013.html
On 05/01/2016 10:39 AM, Martin Sebor wrote:
c/68120 - can't easily deal
Hi,
this patch fixes chkp ICE when we try to inline into an instrumentation thunk.
This is not really a thunk and ths can't be hanled as such.
Bootstrapped/regtested x86_64-linux
Honza
2016-05-16 Jan Hubicka
* ipa-inline-analysis.c (compute_inline_parameters): Disable inlinig
On 05/16/2016 08:12 AM, Nick Clifton wrote:
Hi Guys,
Currently dwarf2out.c:mem_loc_descriptor() has some special case
code to handle the situation where an address is held in a register
whose mode is not of type MODE_INT. It generates a
DW_OP_GNU_regval_type expression which may later o
On 05/13/2016 01:07 PM, Marc Glisse wrote:
Hello,
maybe this would fit better in VRP, but it is easier (and not completely
useless) to put it in match.pd.
Since the transformation is restricted to GIMPLE, I think I don't need
to check that @0 is SSA_NAME. I didn't test if @0 has pointer type
be
On 05/13/2016 06:35 AM, Anton Kolesov wrote:
2016-05-13 Anton Kolesov
* configure.ac: Add ARC support to libgloss.
* configure: Regenerate
Thanks. Installed on the trunk after moving a mis-placed ChangeLog
entry from Wilco.
Jeff
Hi,
in this ICE during error recovery, the check in convert_like_real:
if (CONSTRUCTOR_NELTS (expr) == 0
&& FUNCTION_FIRST_USER_PARMTYPE (convfn) != void_list_node)
is reached for a PARM_DECL as expr. I think that the correct way to
avoid in general such problem is adding (here
On 05/12/2016 10:08 AM, Martin Jambor wrote:
Hi,
the patch below implements deducing aggregate contents from pointers
to constant variables for inlining and IPA-CP, which finally makes us
perform the optimization requested in
https://gcc.gnu.org/ml/gcc/2014-07/msg00240.html. It also lays down
th
On 05/12/2016 10:09 AM, Martin Jambor wrote:
Hi,
the following patch adds the final step necessary to perform
optimization requested in PR 69708, i.e do indirect inlining of a
function passed by value in a structure. It allows jump functions to
be aggregate global constant VAR_DECLs, which enab
On 05/13/2016 01:55 AM, Jakub Sejdak wrote:
+2016-05-13 Jakub Sejdak
+* config.guess: Import version 2016-04-02 (newest).
+* config.sub: Import version 2016-05-10 (newest).
Installed on the trunk. I think this was NAK's for the release branches.
jeff
> As profile-guided optimization can provide very useful information
> about basic block frequencies within a loop, following patch set leverages
> that information. It speeds up a single benchmark from upcoming SPECv6
> suite by 20% (-O2 -profile-generate/-fprofile use) and I think it can
> also i
On 05/10/2016 08:13 AM, David Malcolm wrote:
On Wed, 2016-05-04 at 16:49 -0400, David Malcolm wrote:
[...snip...]
I wrote this by compiling a test.c with -fdump-rtl-all on
x86_64-pc-linux-gnu, and then attempting to load the state at each
pass, and then trying to run just one pass, and fixing b
On Mon, 16 May 2016, Jeff Law wrote:
Please use if (GIMPLE
&& ((get_nonzero_bits ...)
Rather than #if GIMPLE
Richard asked for the reverse in some previous patch:
https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01617.html
I don't really care which one we settle on...
--
Marc Glisse
This is my fifth ping. I just need someone to rubber stamp it so I
can check it in.
Maybe it would be easier if I volunteered to be a doc maintainer so I
can self approve it?
Jim
On Mon, May 9, 2016 at 4:21 PM, Jim Wilson wrote:
> On Mon, May 2, 2016 at 12:13 PM, Jim Wilson wrote:
>> Here is
On 05/16/2016 04:31 PM, Marc Glisse wrote:
On Mon, 16 May 2016, Jeff Law wrote:
Please use if (GIMPLE
&& ((get_nonzero_bits ...)
Rather than #if GIMPLE
Richard asked for the reverse in some previous patch:
https://gcc.gnu.org/ml/gcc-patches/2016-04/msg01617.html
I don't really care w
On 05/04/2016 02:49 PM, David Malcolm wrote:
* The existing RTL code is structured around a single function being
optimized, so, as a simplification, the RTL frontend can only handle
one function per input file. Also, the dump format currently uses
comments to separate functions::
;;
Deletes text claiming that major version changes are rare, and fixes
two misspellings of signaling.
Tested with make info and make dvi.
Jim
2016-05-16 Jim Wilson
* doc/cpp.texi (__GNUC__): Major version changes are no longer rare.
* doc/invoke.texi (-mnan=2008): Change signalling to signali
On 05/16/2016 04:35 PM, Jim Wilson wrote:
This is my fifth ping. I just need someone to rubber stamp it so I
can check it in.
The documentation change looks fine, but as a documentation maintainer
only I don't think I can approve changes to a release branch.
-Sandra
On 05/16/2016 05:05 PM, Jim Wilson wrote:
Deletes text claiming that major version changes are rare, and fixes
two misspellings of signaling.
Tested with make info and make dvi.
This looks fine to me.
-Sandra
Make new functions make_split_prologue_seq, make_prologue_seq, and
make_epilogue_seq.
Tested as in the previous patch; is this okay for trunk?
Segher
2016-05-16 Segher Boessenkool
* function.c (make_split_prologue_seq, make_prologue_seq,
make_epilogue_seq): New functions, f
We should do CLEANUP_EXPENSIVE after shrink-wrapping, because shrink-
wrapping creates constructs that CLEANUP_EXPENSIVE can optimise, and
nothing runs CLEANUP_EXPENSIVE later. We don't need cleanup_cfg before
shrink-wrapping, nothing in shrink-wrapping (or the other *logue insertion
code) cares a
This patch restructures how the prologues/epilogues are inserted. Sibcalls
that run without prologue are now handled in shrink-wrap.c; it communicates
what is already handled by setting the EDGE_IGNORE flag. The
try_shrink_wrapping function then doesn't need to be passed the bb_flags
anymore.
Te
Hi,
static variable all_extensions in aarch64.c is not used and therefore
dead. I don’t see any reason why it should be there. Attached patch
removes this.
Bootstrapped on aarch64-linux-gnu. Regression testing is ongoing.
Is this OK for trunk?
Thanks,
Kugan
gcc/ChangeLog:
2016-05-17 Kugan V
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