Re: [PATCH][RFC][Offloading] Fix PR68463

On Fri, 15 Jan 2016, Ilya Verbin wrote: > Hi! > > Here is my attempt to fix https://gcc.gnu.org/bugzilla/show_bug.cgi?id=68463 > > This patch does 2 things: > > I) lto-plugin doesn't claim files which contain offload sections, but don't > contain LTO sections. Instead, it writes names of files

Re: [doc, 5/n] invoke.texi: add new "Program Instrumentation Options" section

On 01/15/2016 05:17 AM, Sandra Loosemore wrote: > This patch consolidates the documentation of GCC options that add runtime > profiling, error checking, or other instrumentation into a single section. > Currently these are scattered all over, variously classified as debugging > options, code ge

[PATCH, i386] Delay DI mode xor split when expanding comparison

Hi, When scalar-to-vector pass was introduced in i386 target, DI mode instructions split was delayed to split2 pass (was performed on expand before). It appears this causes ~5% degradation on libquantum benchmark. This happens because in original code we have AND and XOR combined into ANDN. Now

Re: [PATCH 3/4 v2] Enhance SCEV to follow copies of SSA_NAMEs.

On Thu, Jan 14, 2016 at 12:30 PM, Richard Biener wrote: > > The vuse test is not necessary > >> + && (gimple_assign_rhs_code (def) == SSA_NAME >> + || is_gimple_min_invariant (gimple_assign_rhs1 (def > > and the is_gimple_min_invariant (rhs1) test is not suffici

Re: [hsa merge 07/10] IPA-HSA pass

> 2016-01-13 Martin Liska > Martin Jambor > > * ipa-hsa.c: New file. > * lto-section-in.c (lto_section_name): Add hsa section name. > * lto-streamer.h (lto_section_type): Add hsa section. > * lto-partition.c: Include "hsa.h" > (add_symbol_to_partition_1

Do not produce debug info during LTO compile stage

Hi, during LTO compile stage we currently build early dwarf debug info just to throw it away. This wastes quite some compile time and memory. Bootstrapped/regtested x86_64-linux, OK? Honza * toplev.c (process_options): Do not produce debug info during LTO compile time. Index: to

Re: [hsa merge 08/10] HSAIL BRIG description header file

On Fri, Jan 15, 2016 at 2:18 AM, Ian Lance Taylor wrote: > Jakub Jelinek writes: > >> On Wed, Jan 13, 2016 at 06:39:33PM +0100, Martin Jambor wrote: >>> the following patch adds a BRIG (binary representation of HSAIL) >>> representation description. It is within a single header file >>> describi

Re: [PATCH 3/4 v2] Enhance SCEV to follow copies of SSA_NAMEs.

On Fri, Jan 15, 2016 at 10:47 AM, Alan Lawrence wrote: > On Thu, Jan 14, 2016 at 12:30 PM, Richard Biener > wrote: > >> >> The vuse test is not necessary >> >>> + && (gimple_assign_rhs_code (def) == SSA_NAME >>> + || is_gimple_min_invariant (gimple_assign_rhs1 (def)

Re: [hsa merge 08/10] HSAIL BRIG description header file

Hi, On Thu, Jan 14, 2016 at 05:18:56PM -0800, Ian Lance Taylor wrote: > Jakub Jelinek writes: > > > On Wed, Jan 13, 2016 at 06:39:33PM +0100, Martin Jambor wrote: > >> the following patch adds a BRIG (binary representation of HSAIL) > >> representation description. It is within a single header

Re: Do not produce debug info during LTO compile stage

On Fri, 15 Jan 2016, Jan Hubicka wrote: > Hi, > during LTO compile stage we currently build early dwarf debug info just to > throw > it away. This wastes quite some compile time and memory. > > Bootstrapped/regtested x86_64-linux, OK? Ok. (did you verify you get the same code / debug out of t

Re: [PATCH, PR69110] Don't return NULL access_fns in dr_analyze_indices

On 13/01/16 09:42, Richard Biener wrote: On Tue, 12 Jan 2016, Tom de Vries wrote: >On 12/01/16 14:04, Richard Biener wrote: > >On Tue, 12 Jan 2016, Tom de Vries wrote: > > > > >On 12/01/16 12:22, Richard Biener wrote: > > > >Doesnt' the same issue apply to > > > > > > > > > >unsigned int *p

Re: [hsa merge 08/10] HSAIL BRIG description header file

On Fri, Jan 15, 2016 at 11:14 AM, Martin Jambor wrote: > Hi, > > On Thu, Jan 14, 2016 at 05:18:56PM -0800, Ian Lance Taylor wrote: >> Jakub Jelinek writes: >> >> > On Wed, Jan 13, 2016 at 06:39:33PM +0100, Martin Jambor wrote: >> >> the following patch adds a BRIG (binary representation of HSAIL)

Re: [PATCH, PR69110] Don't return NULL access_fns in dr_analyze_indices

On Fri, 15 Jan 2016, Tom de Vries wrote: > On 13/01/16 09:42, Richard Biener wrote: > > On Tue, 12 Jan 2016, Tom de Vries wrote: > > > > > >On 12/01/16 14:04, Richard Biener wrote: > > > > > >On Tue, 12 Jan 2016, Tom de Vries wrote: > > > > > > > > > > > > > >On 12/01/16 12:22, Richard Biener wro

Re: [PATCH 1/4] Make SRA scalarize constant-pool loads

On 24/12/15 11:53, Alan Lawrence wrote: Here's a new version that fixes the gcc.dg/guality/pr54970.c failures seen on aarch64 and powerpc64. Prior to SRA handling constant pool decls, -fdump-tree-esra-details (at -O1 -g) had shown: : a = *.LC0; # DEBUG a$0 => MEM[(int[3] *)&*.LC0] a$4

Re: [hsa merge 08/10] HSAIL BRIG description header file

On Fri, Jan 15, 2016 at 11:14:33AM +0100, Martin Jambor wrote: > > Martin, could you ask the HSA Foundation or AMD or whoever if there is > > any way they could remove the second requirement of the license? It > > adds yet another case where anybody distributing GCC has to list yet > > another cop

Re: [PATCH 3/4 v2] Enhance SCEV to follow copies of SSA_NAMEs.

On 15/01/16 10:07, Richard Biener wrote: On Fri, Jan 15, 2016 at 10:47 AM, Alan Lawrence wrote: On Thu, Jan 14, 2016 at 12:30 PM, Richard Biener wrote: The vuse test is not necessary + && (gimple_assign_rhs_code (def) == SSA_NAME + || is_gimple_min_invariant

[PATCH] ARM PR68620 (ICE with FP16 on armeb)

Hi, The attached patch fixes PR68620. It wasn't sufficient to add the movv4hf pattern, because this also enabled other transformations, and I had to update existing support such that the tests continue to pass after using new code paths. I added V4HF/V8HF to the VQXMOV and VDQ iterators to enabl

Re: [PATCH 3/4 v2] Enhance SCEV to follow copies of SSA_NAMEs.

On Fri, Jan 15, 2016 at 11:38 AM, Alan Lawrence wrote: > On 15/01/16 10:07, Richard Biener wrote: >> >> On Fri, Jan 15, 2016 at 10:47 AM, Alan Lawrence >> wrote: >>> >>> On Thu, Jan 14, 2016 at 12:30 PM, Richard Biener >>> wrote: >>> The vuse test is not necessary > +

Re: [PATCH 4/4] Un-XFAIL ssa-dom-cse-2.c for most platforms

It seems the conclusion on PowerPC is to XFAIL the test on powerpc64 (there will be XPASSes with -mcpu=power7 or -mcpu=power8). Which is what the original patch does (https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01979.html). So, Ping. Thanks, Alan On 21/12/15 15:33, Bill Schmidt wrote: On M

Re: [PATCH] sanitize paths used in regular expression

On Thu, 2016-01-14 at 17:31 -0800, Mike Stump wrote: > On Jan 14, 2016, at 4:54 PM, Zachary T Welch wrote: > > This patch fixes a small problem when running 'make check' from a path > > that includes "++". When such paths get used as a regular expression, > > that sequence would cause a runtime e

Re: [PATCH 4/4] Un-XFAIL ssa-dom-cse-2.c for most platforms

On Fri, Jan 15, 2016 at 11:46 AM, Alan Lawrence wrote: > It seems the conclusion on PowerPC is to XFAIL the test on powerpc64 (there > will be XPASSes with -mcpu=power7 or -mcpu=power8). Which is what the > original patch does > (https://gcc.gnu.org/ml/gcc-patches/2015-12/msg01979.html). So, > > P

Re: [PATCH, i386] Delay DI mode xor split when expanding comparison

Hello! > When scalar-to-vector pass was introduced in i386 target, DI mode > instructions split was delayed to split2 pass (was performed > on expand before). It appears this causes ~5% degradation on > libquantum benchmark. This happens because in original code we > have AND and XOR combined in

Make ipa-icf to not prevent devirtualization

Hi, this patch avoid ipa-icf to take away body of a virtual function which is a subject of later devirtualization. Bootstrapped/regtested x86_64-linux, comitted. Honza PR ipa/68148 * ipa-icf.c (sem_function::merge): Virtual functions may become reachable even if they add

Prune BLOCK_VARs lists in free_lang_data

Hi, this is last of my patches to improve partitionability of programs. This patch compacts BLOCK_VARs lists and trows away TYPE_DECLs for -g0 and redundant TYPE_DECLs on all levels. It does make noticeable difference on firefox, but I managed to erase the numbers (can re-test them if requested)

Re: Make ipa-icf to not prevent devirtualization

On Fri, Jan 15, 2016 at 12:01 PM, Jan Hubicka wrote: > Hi, > this patch avoid ipa-icf to take away body of a virtual function which is a > subject > of later devirtualization. But isn't can_remove_if_no_direct_alls_p () supposed to return false then? (depending on cgraph state) Richard. > Boo

Re: Prune BLOCK_VARs lists in free_lang_data

On Fri, 15 Jan 2016, Jan Hubicka wrote: > Hi, > this is last of my patches to improve partitionability of programs. > This patch compacts BLOCK_VARs lists and trows away TYPE_DECLs for -g0 > and redundant TYPE_DECLs on all levels. It does make noticeable difference > on firefox, but I managed to

Re: Make ipa-icf to not prevent devirtualization

> On Fri, Jan 15, 2016 at 12:01 PM, Jan Hubicka wrote: > > Hi, > > this patch avoid ipa-icf to take away body of a virtual function which is a > > subject > > of later devirtualization. > > But isn't can_remove_if_no_direct_alls_p () supposed to return false > then? (depending > on cgraph state

[PATCH] Fix PR68961

Bootstrapped and tested on x86_64-unknown-linux-gnu, applied. Richard. 2016-01-15 Richard Biener PR tree-optimization/68961 * tree-vect-slp.c (vect_analyze_slp_cost_1): Consider cost of invariants in stores again. * gcc.dg/vect/costmodel/x86_64/costmodel-pr68

[PATCH] Fix ICE in vectorizable_store ().

Hello, Thet patch in the bottom adds check if rhs is "useless_type_conversion_p" in vectorizable_store () to avoid subsequent gcc_assert. This change is very similar to [1]. Bootstrapped & regtest in progress. Is it ok for main trunk if regtest pass? gcc/ * tree-vect-stmts.c (vectorizab

Re: [hsa merge 07/10] IPA-HSA pass

On 01/15/2016 10:52 AM, Jan Hubicka wrote: > Do we really need to look that up in the hsa summary? Why these can not be > partitioned the > usual way? Hi. Yes, it's needed as hsa-brig.c uses host function declaration of a kernel as a key for libgomp. That's why we want to put the pair to a LTO

Re: [hsa merge 07/10] IPA-HSA pass

On 01/14/2016 01:58 PM, Jakub Jelinek wrote: > Does it really need to be enabled whenever in_lto_p? > I mean, if HSA is not configured in, I think the gate should be false too. Sure, it can be removed, change will incorporated in final installed version of the file. Thanks, Martin

Re: [PATCH] Fix ICE in vectorizable_store ().

On Fri, 15 Jan 2016, Kirill Yukhin wrote: > Hello, > Thet patch in the bottom adds check if rhs is "useless_type_conversion_p" > in vectorizable_store () to avoid subsequent gcc_assert. > > This change is very similar to [1]. > > Bootstrapped & regtest in progress. > > Is it ok for main trunk i

Re: [hsa merge 08/10] HSAIL BRIG description header file

On Fri, Jan 15, 2016 at 11:37:32AM +0100, Jakub Jelinek wrote: > On Fri, Jan 15, 2016 at 11:14:33AM +0100, Martin Jambor wrote: > > > Martin, could you ask the HSA Foundation or AMD or whoever if there is > > > any way they could remove the second requirement of the license? It > > > adds yet anot

[PATCH] Fix PR69170

I am testing the following to fix PR69170. Bootstrap / regtest running on x86_64-unknown-linux-gnu. Richard. 2016-01-15 Richard Biener PR tree-optimization/69170 * tree-vect-slp.c (vect_build_slp_tree): Verify we are not building a vector from scalar results of a pat

[PATCH] Fix PR66856

With the SLP tree "unsharing" stmts we can get mismatches as to the expected operand ordering in different SLP node "uses". The following patch makes sure we have the same expectation everywhere by only allowing the first SLP use to swap operands. Bootstrap and regtest running on x86_64-unknown-

[PATCH] Fix PR69137

The following patch fixes PR69137 where after the early-debug merge we build DECL_ASSEMBLER_NAME for TYPE_DECLs too early. The fix is easy - just go through the deferred-asm-name machinery. LTO bootstrapped on x86_64-unknown-linux-gnu, testing in progress. Richard. 2016-01-15 Richard Biener

Re: [PATCH] PR target/68991: Add vector_memory_operand and "Bm" constraint

On Tue, Jan 5, 2016 at 8:30 PM, Uros Bizjak wrote: > On Tue, Jan 5, 2016 at 8:20 PM, H.J. Lu wrote: >> On Tue, Jan 5, 2016 at 11:14 AM, Uros Bizjak wrote: >>> On Tue, Jan 5, 2016 at 7:58 PM, H.J. Lu wrote: On Tue, Jan 5, 2016 at 4:32 AM, H.J. Lu wrote: > On Tue, Jan 5, 2016 at 12:11 A

Re: [patch] Rename bits/mutex.h to avoid clashing with glibc

On 06/01/16 13:07 +, Jonathan Wakely wrote: Matthias discovered that the new header I created on trunk clashes with a libc header on GNU/Hurd, so this patch renames it to something unique. This fixes the doxygen comment to match the new filename. Committed to trunk. commit efff85ddad6d4ef

Re: [PATCH] S/390: Add missin full stop in option description.

> gcc/ChangeLog > > * config/s390/s390.opt (mtune): Add full stop. Applied. Thanks! -Andreas-

[PATCH] [ARC] Add basic support for double load and store instructions

Please find attached a patch that adds basic support for double load/store instructions present in archs processors. Ok to apply? //Claudiu gcc/ 2015-01-15 Claudiu Zissulescu * config/arc/arc.c (TARGET_DWARF_REGISTER_SPAN): Define. (arc_init): Check validity mll64 option.

Re: [PATCH, i386, AVX512] PR target/67895: Fix position of embedded rounding/SAE mode in AVX512 vrangep* and vcvt?si2s* instructions.

I've bootstrapped and regtested it against GCC v5 on x86_64-gnu-linux. OK for 5-branch? -- Thanks, Alexander On Fri, Oct 09, 2015 at 05:24:56PM +0300, Kirill Yukhin wrote: > Hello, > On 08 Oct 20:31, Alexander Fomin wrote: > > Hi All, > > > > This patch addresses PR target/67895. For some AVX512

Re: [PATCH] S/390: Better help text for -mmvcle.

> gcc/ChangeLog > > * config/s390/s390.opt (mmvcle): More verbose help text. Applied. Thanks! -Andreas-

Re: [PATCH, ARM] Fix gcc.c-torture/execute/loop-2b.c execution failure on cortex-m0

On Wed, Dec 16, 2015 at 9:11 AM, Thomas Preud'homme wrote: > During reorg pass, thumb1_reorg () is tasked with rewriting mov rd, rn to > subs rd, rn, 0 to avoid a comparison against 0 instruction before doing a > conditional branch based on it. The actual avoiding of cmp is done in > cbranchsi4

Re: [PATCH 0/2] S/390 test case fixes.

> gcc/testsuite/ChangeLog > > * g++.dg/Wframe-address.C: Test requires -mbackchain for s390*-*-* > * g++.dg/Wno-frame-address.C: Ditto. Applied. Thanks! -Andreas-

Re: [PATCH 0/2] S/390 test case fixes.

> gcc/testsuite/ChangeLog > > * gcc.dg/tree-ssa/20040204-1.c: Do not xfail on S/390. Applied. Thanks! -Andreas-

Re: [PATCH 3/2] S/390 test case fixes.

> gcc/testsuite/ChangeLog > > PR c++/56194 > * g++.dg/init/const9.C: Disable test on S/390. Applied. Thanks! -Andreas-

[patch] Fix grammar in extend.texi (Type Traits)

Committed as obvious. commit aa5601c00a7ddd047565956f4a4ceddbc10b4a6a Author: Jonathan Wakely Date: Fri Jan 15 13:12:29 2016 + * doc/extend.texi (Type Traits): Fix grammar. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index b85c34c..a782822 100644 --- a/gcc/doc/extend.texi

[PATCH, committed] Typo fix

Hi, This patch fixes typos in STV pass dumps. Applied to trunk. Thanks, Ilya -- gcc/ 2016-01-15 Ilya Enkovich * config/i386/i386.c (scalar_chain::compute_convert_gain): Fix typo. (convert_scalars_to_vector): Likewise. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i

[PATCH][AArch64] Properly reject invalid attribute strings

Hi all, A bug in the target attribute parsing logic led to us silently accepting attribute strings that did not appear in the attributes table i.e invalid attributes. This patch fixes that oversight so we now error out on obviously bogus strings. Bootstrapped and tested on aarch64. Ok for tru

IRA fix for 47992

This is a report of a crash in IRA. If you debug it with a sufficiently old compiler, you'll find that we manage to delete some basic blocks from within IRA. Later on, reload calls alter_reg for all unallocated pseudos, including one that only occurs in the deleted blocks. reload does not notic

Re: reject decl with incomplete struct/union type in check_global_declaration()

On 15 January 2016 at 03:27, Joseph Myers wrote: > On Thu, 14 Jan 2016, Prathamesh Kulkarni wrote: > >> Hi, >> For test-case containing only the following declaration: >> static struct undefined_struct object; >> gcc rejects it at -O0 in assemble_variable() with error "storage size >> of is unkno

Re: [openacc] implicit non-scalars data mapping in kernels

On 01/14/16 18:10, Jakub Jelinek wrote: On Thu, Jan 14, 2016 at 03:02:28PM -0800, Cesar Philippidis wrote: Is this a case of the Fortran FE OpenACC bits not annotating some artificial object correctly? I don't think it's specific to fortran. You can have reference types in c++ too. Actually, J

[PATCH, PR68976] Use reaching def phi arg in sese_add_exit_phis_edge

Hi, Consider testcase test.c: ... int kw = -1, hv = -1, ju; int mc[1]; void foo (void) { for (; kw; ++kw) for (; hv; ++hv) for (ju = 0; ju < 2; ++ju) mc[kw+1] = mc[0]; } ... When compiled with -O2 -fgraphite-identity, we run into an ICE: ... test.c: In function ‘foo’: test.c:5:1

Re: [PATCH 4/2] S/390 test case fixes.

> gcc/testsuite/ChangeLog > > * gfortran.dg/bind_c_array_params_2.f90: Fix test patterns for S/390. Applied. Thanks! -Andreas-

Re: [PATCH] PR target/68991: Add vector_memory_operand and "Bm" constraint

On Fri, Jan 15, 2016 at 01:36:40PM +0100, Richard Biener wrote: > >> My patches only change SSE patterns without ssememalign > >> attribute, which defaults to > >> > >> (define_attr "ssememalign" "" (const_int 0)) > > > > The patch is OK for mainline. > > > > (subst.md changes can IMO be considered

Re: [PATCH] PR target/68991: Add vector_memory_operand and "Bm" constraint

On Fri, Jan 15, 2016 at 6:11 AM, Jakub Jelinek wrote: > On Fri, Jan 15, 2016 at 01:36:40PM +0100, Richard Biener wrote: >> >> My patches only change SSE patterns without ssememalign >> >> attribute, which defaults to >> >> >> >> (define_attr "ssememalign" "" (const_int 0)) >> > >> > The patch is O

[PATCH 1/2][AArch64] Implement AAPCS64 updates for alignment attribute

gcc/ChangeLog: * gcc/config/aarch64/aarch64.c (aarch64_function_arg_alignment): Rewrite, looking one level down for records and arrays. --- gcc/config/aarch64/aarch64.c | 32 +--- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/gcc/confi

[PATCH 0/2][AArch64] Implement AAPCS64 updates for alignment attribute

These parallel the updates to ARM https://gcc.gnu.org/ml/gcc-patches/2015-07/msg00214.html following from Richard Earnshaw's proposal for updates to the AAPCS and AAPCS64, https://gcc.gnu.org/ml/gcc/2015-07/msg00040.html . On AArch64 we do not have the problem of broken profiledbootstrap (as orig

[PATCH 2/2][AArch64] Tests of AAPCS64 updates for alignment attribute

Here I've added both tests using the abitest.h framework(which verifies values are passed in the correct registers as specified by the AAPCS64), and separate tests which verify that called functions read arguments from the same locations as they are passed. Hence, each test_align-N.c corresponds to

Re: [PATCH] PR target/68991: Add vector_memory_operand and "Bm" constraint

On Fri, Jan 15, 2016 at 6:16 AM, H.J. Lu wrote: > On Fri, Jan 15, 2016 at 6:11 AM, Jakub Jelinek wrote: >> On Fri, Jan 15, 2016 at 01:36:40PM +0100, Richard Biener wrote: >>> >> My patches only change SSE patterns without ssememalign >>> >> attribute, which defaults to >>> >> >>> >> (define_attr

PR 69246: Invalid REG_ARGS_SIZE for sibcalls

The problem in this PR was that we were treating a sibcall as popping arguments, leading to a negative REG_ARGS_SIZE. It doesn't really make sense to treat sibcalls as popping since (a) they're deallocating the caller's stack, not ours, and (b) there are no optabs for popping sibcalls (any more).

Re: [PATCH] PR target/68991: Add vector_memory_operand and "Bm" constraint

On Fri, Jan 15, 2016 at 06:24:42AM -0800, H.J. Lu wrote: > >> -Ofast -mavx -mno-avx2 -mtune=bdver2 > >> > >> float *a, *b; > >> int c, d, e, f; > >> void > >> foo (void) > >> { > >> for (; c; c++) > >> a[c] = 0; > >> if (!d) > >> for (; c < f; c++) > >> b[c] = (double) e / b[c]; >

Re: PR 69246: Invalid REG_ARGS_SIZE for sibcalls

On 01/15/2016 03:31 PM, Richard Sandiford wrote: The problem in this PR was that we were treating a sibcall as popping arguments, leading to a negative REG_ARGS_SIZE. It doesn't really make sense to treat sibcalls as popping since (a) they're deallocating the caller's stack, not ours, and (b) th

Re: [PATCH] DWARF: add abstract origin links on lexical blocks DIEs

On 01/13/2016 01:17 PM, Richard Biener wrote: I wonder if you can construct a guality testcase that passes with and fails without the patch? I’ve tried to first look at how guality testcases are written (thanks for your answers on IRC, by the way :-)) and then how I could write a testcase for

Re: [hsa merge 05/10] OpenMP lowering/expansion changes (gridification)

Thanks Jakub and Alex, I have committed the following to the branch to address your comments: 2016-01-15 Martin Jambor * gimple.h: Fixed comment of gimple_statement_omp_single_layout * omp-low.c (get_target_argument_value): Fixed spelling in its comment. (push_

Re: [hsa merge 07/10] IPA-HSA pass

On Thu, Jan 14, 2016 at 01:58:58PM +0100, Jakub Jelinek wrote: > Otherwise LGTM. > > Jakub Thanks Jakub, I have committed the following patch from Martin Liska that addresses your comments. Martin 2016-01-15 Martin Liska * ipa-hsa.c (process_hsa_functions): Fixed coding style.

[gomp4] implicit non-scalars data mapping in kernels backport

I've backported this patch from trunk to gomp-4_0-branch which teaches the gimplifier to inspect the type of the value being pointed to when deciding what type of implicit data mapping is necessary for a variable. More discussing on this patch can be found here

Re: [hsa merge 07/10] IPA-HSA pass

On Fri, Jan 15, 2016 at 03:53:23PM +0100, Martin Jambor wrote: > @@ -317,7 +319,7 @@ public: > bool > pass_ipa_hsa::gate (function *) > { > - return hsa_gen_requested_p () || in_lto_p; > + return hsa_gen_requested_p (); > } > > } // anon namespace I actually didn't mean this, I mean more

[PATCH][ARM] PR target/69135: Mark ARMv8 vcvt instructions as unconditional

Hi all, In this PR the ARMv8 vcvt instructions end up being conditionalised when they don't have a conditional form. setting the predicable attribute to "no" is not enough. We need to set the "conds" attribute to unconditional as well. Bootstrapped and tested on arm-none-linux-gnueabihf. Ok fo

Re: [hsa merge 09/10] Majority of the HSA back-end

Hi, thanks Jakub. Below you'll find a patch, which is mostly work of Martin Liska, that should address all the review comments. We have then also went over the "XXX" marks (my bad that I forgot that Michael uses this mark), removed half of them and turned the rest into TODOs. Let me just quickl

Re: [hsa merge 10/10] HSA register allocator

Hi, On Thu, Jan 14, 2016 at 03:41:34PM +0100, Jakub Jelinek wrote: > On Wed, Jan 13, 2016 at 06:39:35PM +0100, Martin Jambor wrote: > > +for (phi = hbb->m_first_phi; > > +phi; > > +phi = phi->m_next ? as_a (phi->m_next): NULL) > > Space before : > > Ok with that change. > I have c

Re: [hsa merge 09/10] Majority of the HSA back-end

On Fri, Jan 15, 2016 at 04:08:14PM +0100, Martin Jambor wrote: > We don't error, apart from issuing a warning we basically ignore them. > I believe we can do it even in the long term and that it is in fact > useful because the standard says that the "effect" if these routines > is "unspecified" if

[PATCH, i386] Support ANDN in stv pass

Hi, This patch continues resolving andn regression case in stv pass (see https://gcc.gnu.org/ml/gcc-patches/2016-01/msg01017.html). In this patch a new andn pattern added similar to other bit DI patterns we have for stv pass. This improves performance of 462.libquantum benchmark on Haswell (+2.6%

C++ PATCH for c++/68847 (ICE with builtin in template)

The delayed folding code for builtins needs to make sure that the expression is instantiated before we try to fold it, because we can get here while parsing a template. Tested x86_64-pc-linux-gnu, applying to trunk. commit 6e41de9cec949bc7c09406b50105afee927a0ae3 Author: Jason Merrill Date:

Re: [doc, 5/n] invoke.texi: add new "Program Instrumentation Options" section

On 01/15/2016 01:39 AM, Mikhail Maltsev wrote: On 01/15/2016 05:17 AM, Sandra Loosemore wrote: This patch consolidates the documentation of GCC options that add runtime profiling, error checking, or other instrumentation into a single section. Currently these are scattered all over, variously

Re: [PATCH] DWARF: add abstract origin links on lexical blocks DIEs

On Fri, Jan 15, 2016 at 3:41 PM, Pierre-Marie de Rodat On 01/13/2016 01:17 PM, Richard Biener wrote: >> >> I wonder if you can construct a guality testcase that passes with and >> fails without >> the patch? > > > I’ve tried to first look at how guality testcases are written (thanks for > your ans

C++ PATCH for c++/69257 (ICE with incomplete deref and asm)

In this testcase, the compiler fails to diagnose trying to use the value of an INDIRECT_REF of incomplete type. Since decay_conversion is modeling the lvalue->rvalue conversion here, that seems a logical place to complain. When making that change, I noticed that we were incorrectly calling m

Re: [hsa merge 07/10] IPA-HSA pass

Hi, On Fri, Jan 15, 2016 at 04:01:49PM +0100, Jakub Jelinek wrote: > On Fri, Jan 15, 2016 at 03:53:23PM +0100, Martin Jambor wrote: > > @@ -317,7 +319,7 @@ public: > > bool > > pass_ipa_hsa::gate (function *) > > { > > - return hsa_gen_requested_p () || in_lto_p; > > + return hsa_gen_requeste

PR68609

My initial implementation of software sqrt based on estimate was fragile for denormal inputs. This revised version converts both sqrt and rsqrt to use Goldschmidt's Algorithm and calculates sqrt through an iterative correction to a sqrt estimate. Because sqrt only is profitable for 1 iteration, t

Re: [hsa merge 07/10] IPA-HSA pass

On Fri, Jan 15, 2016 at 05:02:34PM +0100, Martin Jambor wrote: > How do other accelerators cope with the situation when half of the > application is compiled with the accelerator disabled? (Would some of > their calls to GOMP_target_ext lead to abort?) GOMP_target_ext should never abort (unless i

Re: IRA fix for 47992

On 01/15/2016 06:42 AM, Bernd Schmidt wrote: This is a report of a crash in IRA. If you debug it with a sufficiently old compiler, you'll find that we manage to delete some basic blocks from within IRA. Later on, reload calls alter_reg for all unallocated pseudos, including one that only occurs i

Re: [hsa merge 07/10] IPA-HSA pass

On Fri, Jan 15, 2016 at 17:09:54 +0100, Jakub Jelinek wrote: > On Fri, Jan 15, 2016 at 05:02:34PM +0100, Martin Jambor wrote: > > How do other accelerators cope with the situation when half of the > > application is compiled with the accelerator disabled? (Would some of > > their calls to GOMP_tar

Re: [hsa merge 07/10] IPA-HSA pass

On Fri, Jan 15, 2016 at 07:38:14PM +0300, Ilya Verbin wrote: > On Fri, Jan 15, 2016 at 17:09:54 +0100, Jakub Jelinek wrote: > > On Fri, Jan 15, 2016 at 05:02:34PM +0100, Martin Jambor wrote: > > > How do other accelerators cope with the situation when half of the > > > application is compiled with

Thoughts on memcmp expansion (PR43052)

PR43052 is a PR complaining about how the rep cmpsb expansion that gcc uses for memcmp is slower than the library function. As is so often the case, if you investigate a bit, you can find a lot of issues with the current situation in the compiler. This PR was accidentally fixed by a patch by N

[PATCH 01/15] add more coalescing to simplify constraints

From: Sebastian Pop 2015-12-30 Aditya Kumar Sebastian Pop * graphite-dependences.c (constrain_domain): Add call to isl_*_coalesce. (add_pdr_constraints): Same. (scop_get_reads): Same. (scop_get_must_writes): Same. (scop_get_may_writes): Sa

[PATCH 04/15] add missing ast node for isl 0.15

From: Sebastian Pop * graphite-isl-ast-to-gimple.c (translate_isl_ast): Also handle isl_ast_node_mark. --- gcc/graphite-isl-ast-to-gimple.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/gcc/graphite-isl-ast-to-gimple.c b/gcc/graphite-isl-ast-to-gimple.c index d143ef7

Re: [PATCH, PR68976] Use reaching def phi arg in sese_add_exit_phis_edge

On Fri, Jan 15, 2016 at 7:58 AM, Tom de Vries wrote: > During scop detection/canonicalize_loop_closed_ssa_form, an exit phi is > introduced in the loop for _24: > ... > : > # _58 = PHI <_24(22)> > ... > Note that _24 is not defined in the loop, but before it. AFAIU the header > comment of cano

Re: [PATCH][AArch64] Properly reject invalid attribute strings

On Fri, Jan 15, 2016 at 01:39:54PM +, Kyrill Tkachov wrote: > Hi all, > > A bug in the target attribute parsing logic led to us silently accepting > attribute strings that did not appear in the attributes table i.e invalid > attributes. > > This patch fixes that oversight so we now error out

[PATCH 09/15] fix memory leak in scop-detection

From: Sebastian Pop * graphite-scop-detection.c (scop_detection::harmful_loop_in_region): Free dom and loops. (scop_detection::loop_body_is_valid_scop): Free bbs. --- gcc/graphite-scop-detection.c | 14 +++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff

[PATCH 07/15] check that all loops are valid in the combined region

From: Sebastian Pop the bug was exposed by rewriting an if condition into an assert in the computation of the loop iteration domains. * graphite-scop-detection.c (loop_is_valid_scop): Renamed loop_is_valid_in_scop. (scop_detection::harmful_stmt_in_region): Renamed harmful_loop

[PATCH 03/15] fix PR68343: disable graphite tests for isl 0.14 or earlier

From: Aditya Kumar The patch disables all optimizations when configuring gcc with isl 0.14 or earlier. The next patch makes use of the schedule-trees that is only availaible in isl 0.15. ChangeLog: * Makefile.in: Regenerate. * Makefile.tpl: Export ISLVER. * configure:

Re: [PATCH][AArch64] Handle compare of zero_extract form of TST-immediate in rtx costs

On Mon, Jan 11, 2016 at 04:41:22PM +, Kyrill Tkachov wrote: > Hi all, > > The test gcc.target/aarch64/tst_3.c fails for an explicit -mcpu=cortex-a53 > because we don't handle the recent compare with zero_extract pattern properly > in rtx costs, so we end up recursing into its operands and end

[PATCH 11/15] check for unstructured control flow

From: Sebastian Pop * graphite-scop-detection.c (scop_detection::harmful_loop_in_region): Discard unstructured if-then-else regions. --- gcc/graphite-scop-detection.c | 12 1 file changed, 12 insertions(+) diff --git a/gcc/graphite-scop-detection.c b/gcc/graphite-sc

[PATCH 06/15] fix codegen error exposed by compute isl flow patch

From: Sebastian Pop we used to fail using an iv from a different loop. * graphite-isl-ast-to-gimple.c (enum phi_node_kind): New. (class translate_isl_ast_to_gimple): Use phi_node_kind instead of bool. (is_valid_rename): Same. (translate_isl_ast_to_gimple::get_rena

[PATCH 02/15] remove unused variable

From: Sebastian Pop 2015-12-30 Sebastian Pop * graphite-poly.c (new_poly_bb): Remove use of PBB_IS_REDUCTION. * graphite.h (struct poly_bb): Remove field is_reduction. (PBB_IS_REDUCTION): Remove. --- gcc/graphite-poly.c | 1 - gcc/graphite.h | 4 2 files cha

Re: [hsa merge 08/10] HSAIL BRIG description header file

On Fri, Jan 15, 2016 at 01:03:35PM +0100, Jakub Jelinek wrote: > On Fri, Jan 15, 2016 at 11:37:32AM +0100, Jakub Jelinek wrote: > > On Fri, Jan 15, 2016 at 11:14:33AM +0100, Martin Jambor wrote: > > > > Martin, could you ask the HSA Foundation or AMD or whoever if there is > > > > any way they coul

[PATCH 05/15] remove tiling

From: Sebastian Pop We remove all code related to tiling, then we will call isl functionality for that. * graphite-isl-ast-to-gimple.c (set_options_for_schedule_tree): Remove. (translate_isl_ast_to_gimple::scop_to_isl_ast): Call set_separate_option. (graphite_regenerate

[PATCH 12/15] new scop schedule.

From: Sebastian Pop * graphite-dependences.c (scop_get_reads): Do not call isl_union_map_add_map that is undocumented isl functionality. (scop_get_must_writes): Same. (scop_get_may_writes): Same. (scop_get_original_schedule): Remove. (scop_get_depen

[PATCH 13/15] reinstantiate loop blocking

* graphite-optimize-isl.c (get_schedule_for_node_st): Add back. (optimize_isl): Call isl_schedule_map_schedule_node_bottom_up. * params.def (PARAM_LOOP_BLOCK_TILE_SIZE): Adjust to 32. gcc/testsuite * gcc.dg/graphite/block-1.c: * gcc.dg/graphite/block-5.c:

[PATCH 08/15] record loops in execution order

From: Sebastian Pop * graphite-scop-detection.c (record_loop_in_sese): New. (gather_bbs::before_dom_children): Call record_loop_in_sese. (build_scops): Remove call to build_sese_loop_nests. * sese.c (sese_record_loop): Remove. (build_sese_loop_nests): Remov

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