On Tue, Feb 25, 2014 at 7:10 AM, Gopalasubramanian, Ganesh
wrote:
> I could see "storent" pattern in x86 machine descriptions (in sse.md)., but
> internals doc don't mention it. Should we add a description about this in the
> internals doc?
This pattern was added way back in 2007 and was not do
The original patch http://gcc.gnu.org/ml/gcc-patches/2007-04/msg01862.htm
Thanks,
Andrew Pinski
> On Feb 25, 2014, at 12:00 AM, Uros Bizjak wrote:
>
> On Tue, Feb 25, 2014 at 7:10 AM, Gopalasubramanian, Ganesh
> wrote:
>> I could see "storent" pattern in x86 machine descriptions (in sse.md).,
On Mon, 24 Feb 2014, Jan Hubicka wrote:
> >
> > This addresses miscompilations caused by improperly mixing
> > -f[no-]strict-overflow units (and thus optimize <= 1 and optimize >= 2
> > units!). It does so by merging -f[no-]strict-overflow and the
> > related -f[no-]wrapv and -f[no-]trapv conser
On 21 Feb 18:35, Uros Bizjak wrote:
> On Fri, Feb 21, 2014 at 4:25 PM, Ilya Tocar wrote:
> >> > Latest version of AVX512 spec
> >> > http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
> >> > Has a few changes.
> >> >
> >> > 1)PREFETCHWT1 instruction now has separat
Andrey Belevantsev writes:
> Fixed by placing the initialization properly at the end of sched_rgn_init
> and also moving the check for sched_pressure != NONE outside of the if
> statement in schedule_region as discussed in the PR trail with Jakub.
>
> Bootstrapped and tested on x86-64, ok?
This
Hi,
Current value for max_insns_skipped is 6. For THUMB2, it needs 2 (IF-THEN)
or 3 (IF-THEN-ELSE) IT blocks to hold all the instructions. The overhead of
IT is 4 or 6 BYTES.
If we do not generate IT blocks, for IF-THEN, the overhead of conditional
jump is 2 or 4; for IF-THEN-ELSE, the overhead i
On 25.02.2014 13:14, Andreas Schwab wrote:
Andrey Belevantsev writes:
Fixed by placing the initialization properly at the end of sched_rgn_init
and also moving the check for sched_pressure != NONE outside of the if
statement in schedule_region as discussed in the PR trail with Jakub.
Bootstra
On Tue, Feb 25, 2014 at 10:13 AM, Ilya Tocar wrote:
>> >> > Latest version of AVX512 spec
>> >> > http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
>> >> > Has a few changes.
>> >> >
>> >> > 1)PREFETCHWT1 instruction now has separate CPUID bit PREFETCHWT1.
>> >>
Hi all,
A while back I sent a patch to fix this PR
(http://gcc.gnu.org/ml/gcc-patches/2014-02/msg00652.html) by generalising the
neon_vld1_dupv2di splitter. There is an alternative safer approach at this
stage, which is to relax CANNOT_CHANGE_MODE_CLASS to allow conversions from 128
to 64-bit
Hi,
here we ICE exactly as we did in c++/53756: the only difference is the
use of decltype(auto) instead of auto. Now, if we compare is_cxx_auto to
is_auto (the front-end helper), evidently there is an inconsistency
about the handling of decltype(auto) and the below fixes the ICE.
However, al
Hi all,
The problem solved in this patch is that when gcc is configured with
--with-arch=armv8-a gcc will go into aarch64-arches.def, pick the
representative CPU (Cortex-A53 for ARMv8-A) and use that CPUs ISA flags. Now
that we specified that Cortex-A53 has CRC and crypto though, this means t
On 25/02/14 09:56, Kyrill Tkachov wrote:
> Hi all,
>
> A while back I sent a patch to fix this PR
> (http://gcc.gnu.org/ml/gcc-patches/2014-02/msg00652.html) by generalising the
> neon_vld1_dupv2di splitter. There is an alternative safer approach at this
> stage, which is to relax CANNOT_CHANGE
On 25/02/14 10:08, Kyrill Tkachov wrote:
2014-02-25 Kyrylo Tkachov
* config.gcc (aarch64*-*-*): Use ISA flags from aarch64-arches.def.
Do not define target_cpu_default2 to generic.
* config/aarch64/aarch64.h (TARGET_CPU_DEFAULT): Use generic cpu.
* config/aarch64/aarc
On Tue, Feb 25, 2014 at 6:12 AM, bin.cheng wrote:
> Hi,
> This patch is to fix regression reported in PR60280 by removing forward loop
> headers/latches in cfg cleanup if possible. Several tests are broken by
> this change since cfg cleanup is shared by all optimizers. Some tests has
> already b
PR57936 is regarding a reload problem with rs6000_secondary_reload_inner.
This is the failing instruction, as at the start of reload:
(insn 61 60 62 3 (set (reg:V16QI 220)
(unspec:V16QI [
(subreg:V16QI (reg:V2DI 159 [ D.2446 ]) 0)
(subreg:V16QI (reg:V2DI 15
Updated as comments.
Thanks,
bin
> -Original Message-
> From: Richard Biener [mailto:richard.guent...@gmail.com]
> Sent: Tuesday, February 25, 2014 6:38 PM
> To: Bin Cheng
> Cc: GCC Patches
> Subject: Re: [PATCH GCC]Allow cfgcleanup to remove forwarder loop
> preheaders and latches
>
> O
On Tue, Feb 25, 2014 at 12:20 PM, bin.cheng wrote:
> Updated as comments.
Ok.
Thanks,
Richard.
> Thanks,
> bin
>
>> -Original Message-
>> From: Richard Biener [mailto:richard.guent...@gmail.com]
>> Sent: Tuesday, February 25, 2014 6:38 PM
>> To: Bin Cheng
>> Cc: GCC Patches
>> Subject:
Hi,
This patch fixes a bug in vshr_n_u64 and vshrd_n_u64 intrinsic
behavior in case of shift by 64. Shift by 64 is strictly defined in ACLE
to use ushr instruction intended by those intrinsics.
The testcase provided also tests the behavior for intrinsics mentioned
above with values other then
Hi
I added a comment to cpplib.h file for understanding.
Thanks.
Added a comment to cpplib.h file.
Index: cpplib.h
===
--- cpplib.h (revision 208118)
+++ cpplib.h (working copy)
@@ -103,7 +103,7 @@
OP(SEMICOLON, ";") /* structure */\
OP(ELLIPSIS, "...") \
OP(PLUS_PLUS, "++") /*
Alan Modra wrote:
> Normally, reload 2, the secondary reload for reload 3, would result in
> a call to reload_v16qi_si_load with (reg:V16QI 78 1) as its "reg"
> argument, and the mem home for pseudo reg 159 as its "mem" arg.
>
> However, reload1.c:choose_reload_regs has code to, as the comment
>
This fixes the ICE on our regular -flto-partition=none testers
which sees an edge w/o call-stmt after inlining (see the PR
for details). I'm not sure this is supposed to happen but the
following re-instantiates the guard to inline_update_overall_summary
which was present before the last change to
On Tue, Feb 25, 2014 at 02:30:59PM +0100, Ulrich Weigand wrote:
> Alan Modra wrote:
>
> > Normally, reload 2, the secondary reload for reload 3, would result in
> > a call to reload_v16qi_si_load with (reg:V16QI 78 1) as its "reg"
> > argument, and the mem home for pseudo reg 159 as its "mem" arg.
This patch simplifies the entity resolution machinery which detects an illegaly
used SPARK volatile object with enabled external properties Async_Writers or
Effective_Reads. The mechanism no longer traverses the parent chain as this is
not needed.
-- Source --
-- volati
On 25-Feb-14 01:21, Jeff Law wrote:
I think this should be queued until after 4.9 branches. It's adding a
new capability (posix threading on vxworks), not fixing a bug and
certainly not fixing a regression AFAICT.
Fair enough. It just seems somewhat trivial to me, as it doesn't add
any funct
This patch plugs several memory leaks involving Ada 2012 iterator loops by
properly managing the secondary stack at each iteration of the loop.
-- Source --
-- iterator_leak.adb
with Ada.Containers; use Ada.Containers;
with Ada.Containers.Vectors;
with Ada.Text_IO;
Hi David,
Thanks. I have this upstream for mainline now. This problem appears to
have been introduced in GCC 4.6. Is it ok to backport this fix to the
FSF 4.7 and 4.8 branches?
Thanks,
Bill
On Mon, 2014-02-24 at 23:29 -0500, David Edelsohn wrote:
> On Mon, Feb 24, 2014 at 9:13 PM, Bill Schmid
This patch reimplements the support for SPARK aspects/pragmas that apply to a
subprogram body stub and implements a missing rule which forbids the placement
of refinement annotations in subunits.
-- Source --
-- error.ads
package Error
with SPARK_Mode => On,
This implements a new pragma Warning_As_Error which can be used to
specify that selected warnings are to be treated as errors. See
new documentation in GNAT RM for full details.
The pragma can appear either in a global configuration pragma file
(e.g. gnat.adc), or at the start of a file. Given a g
Hi all,
This is an optimization patch which will combine "ubfiz" and "orr"
insns with a single "bfi" when certain conditions meet.
tmp = (x & m) | ( (y & n) << lsb) can be presented using
and tmp, x, m
bfi tmp, y, #lsb, #width
if ((n+1) == 2^width) && (m & n << lsb) == 0.
The origi
No_Dynamic_Attachment is now enforced in -gnatc mode, and includes
checking for any use of any of the entities, including rename and
access. No_Abort_Statements now checks for any use of Abort_Task,
including renaming. The following test programs are compiled using
-gnatc -gnatj55.
1. pragma
On 20 Feb 17:23, Uros Bizjak wrote:
> On Thu, Feb 20, 2014 at 4:39 PM, Ilya Tocar wrote:
>
> > Latest version of AVX512 spec
> > http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
> > Has a few changes.
> > 2)Currently for scatter/gather prefetches intrinsics we
On 2014-02-06 21:18, Benno Schulenberg wrote:
> Updating a bit the Dutch translations of GCC's messages,
> I noticed the following mistakes in three msgids:
>
> "only displayed one" ==> "displayed only once"
> "none class-method" ==> "non-class method"
> "incorect" ==> "incorrect"
Pin
On 2014-02-07 14:48, Benno Schulenberg wrote:
> The below fixes some more typos in GCC's error messages.
> When found okay, please apply.
Ping?
> 2014-02-07 Benno Schulenberg
>
> * config/arc/arc.c (arc_init): Fix typo in error message.
> * config/i386/i386.c (ix86_expand_builtin)
On Tue, Feb 25, 2014 at 10:15 AM, Bill Schmidt
wrote:
> Hi David,
>
> Thanks. I have this upstream for mainline now. This problem appears to
> have been introduced in GCC 4.6. Is it ok to backport this fix to the
> FSF 4.7 and 4.8 branches?
This is okay to backport.
Thanks, David
On Tue, Feb 25, 2014 at 5:04 PM, Ilya Tocar wrote:
>> > Latest version of AVX512 spec
>> > http://download-software.intel.com/sites/default/files/managed/50/1a/319433-018.pdf
>> > Has a few changes.
>
>> > 2)Currently for scatter/gather prefetches intrinsics we accept 1 as
>> > possible hint para
Hi,
This patch introduces vreinterpret implementation for 64-bit float
vectors intrinsics and adds testcase for them.
This patch tested on LE or BE with no regressions.
Is this patch ok for stage-1?
Thanks,
Alex
gcc/
2014-02-14 Alex Velenko
* config/aarch64/aarch64-builtins.c (aa
On 02/25/2014 07:56 AM, Renlin Li wrote:
> +(define_insn_and_split "*combine_bfi3"
> + [(set (match_operand:GPI 0 "register_operand" "=r")
> +(ior:GPI (and:GPI (match_operand:GPI 1 "register_operand" "0")
> + (match_operand 2 "const_int_operand" "n"))
> +
On Feb 24, 2014, at 2:04 AM, Zhenqiang Chen wrote:
>
>> all of your testcases have mixed C++/C comments for the dg-do line.
>> Please use pure C comments instead.
>
> Thanks for the comments! Updated.
Ok.
On 02/25/14 01:23, Andrew Pinski wrote:
On Wed, Dec 4, 2013 at 10:12 AM, Yufeng Zhang wrote:
On 12/03/13 21:24, Andrew Pinski wrote:
[snip]
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 313517f..08fcc94 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/
On 02/25/2014 09:02 AM, Alex Velenko wrote:
> +(define_expand "aarch64_reinterpretdf"
> + [(match_operand:DF 0 "register_operand" "")
> + (match_operand:VD_RE 1 "register_operand" "")]
> + "TARGET_SIMD"
> +{
> + aarch64_simd_reinterpret (operands[0], operands[1]);
> + DONE;
> +})
I believe y
Committed to branch dmalcolm/jit:
With this commit, it's possible to inspect local variables in the debugger
when stepping through a JIT-generated function.
gcc/jit/
* internal-api.h (gcc::jit::playback::function): Add field
m_inner_block.
* internal-api.c (gcc::jit::play
The primary bug under discussion in 53808 has been fixed separately, but
it also pointed out that once devirtualization resolves the delete to
use the bar destructor, we ought to be able to inline that destructor.
So if we're devirtualizing, always add a virtual defaulted dtor to the
list of fu
My initial implementation of alias template equivalence failed to handle
the case here, of a nested alias being equivalent to its enclosing class
template. Fixed by implementing the rules in the standard more directly.
Tested x86_64-pc-linux-gnu, applying to trunk.
commit f7c8a08b6ee7f9229be75
Committed to branch dmalcolm/jit:
gcc/jit/
* libgccjit.h (gcc_jit_function_add_void_return): New.
* libgccjit.map (gcc_jit_function_add_void_return): New.
* libgccjit.c (gcc_jit_function_add_void_return): New.
* libgccjit++.h (add_return): Add overloaded variant wit
Not sure if this is a good idea, I thought it would be better to
replace #else #if by #elif.
* hard-reg-set.h: Replace #else #if by #elif.
Bootstrapped on x86_64-unknown-linux-gnu.
Ok for trunk ?
Thanks and Regards,
Prathamesh
Index: gcc/hard-reg-set.h
My earlier patch didn't go far enough; when we apply a name for linkage
purposes and fix up the visibility of the type, we also need to fix up
the visibility and names of any members and implementation bits.
At first I thought we would need to deal with static data members as
well as functions
Getting the reference binding rules for C++11 right (in the standard)
has taken quite a few iterations. I'm pretty happy with the latest
wording, which deals with user-defined conversions by recursing on the
result of the conversion. This patch implements those rules. I'm a
little uncertain
>
> This fixes the ICE on our regular -flto-partition=none testers
> which sees an edge w/o call-stmt after inlining (see the PR
> for details). I'm not sure this is supposed to happen but the
> following re-instantiates the guard to inline_update_overall_summary
> which was present before the la
Hi,
With ILP32 AARCH64, Pmode (DImode) != ptrmode (SImode) so the
variable decl
has a mode of SImode while the register is DImode. So the target that gets
passed down to expand_builtin_thread_pointer is NULL as expand does not
know how to get a subreg for a pointer type.
On Tue, 2014-02-25 at 11:23 -0500, David Edelsohn wrote:
> On Tue, Feb 25, 2014 at 10:15 AM, Bill Schmidt
> wrote:
> > Hi David,
> >
> > Thanks. I have this upstream for mainline now. This problem appears to
> > have been introduced in GCC 4.6. Is it ok to backport this fix to the
> > FSF 4.7
Hi There,
As the assembler directive ".code 16" equals ".thumb", this small patch is
going to redefine the ASM_APP_OFF in a cleaner way. Tested with GCC
regression test and no regressions. Is it OK to current trunk or shall we
wait until the release-branch mode end?
BR,
Terry
2014-02-25 Terry G
Hi,
Just like most of the targets out there we should define
TRY_EMPTY_VM_SPACE to have better PCH support.
OK? Built and tested on aarch64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
* config/host-linux.c (TRY_EMPTY_VM_SPACE): Change aarch64 ilp32
definition.
---
g
This patch set adds ILP32 support to GCC for GNU/Linux.
A patch which adds the host support for PCH.
A patch which fixes TLS variables with ILP32; shows up while compiling glibc
so no new testcases added.
One final patch which adds the name of the dynamic linker and passes the linker
script to
Hi,
This is the final patch which adds support for the dynamic linker and
multi-lib directories for ILP32. I did not change multi-arch support as
I did not know what it should be changed to and internally here at Cavium,
we don't use multi-arch. Updated for the new names that were decided on.
Hi,
With ILP32, some simple usage of TLS variables causes an unrecognizable
instruction due to needing to use SImode for loading pointers from memory.
This fixes the three (tlsie_small, tlsle_small, tlsdesc_small) patterns to
support SImode for pointers. I modified them to be like what was done
On Wed, Feb 26, 2014 at 01:03:52AM +1030, Alan Modra wrote:
> On Tue, Feb 25, 2014 at 02:30:59PM +0100, Ulrich Weigand wrote:
> > Instead, there's code in emit_input_reload_insns that is supposed
> > to re-check whether a secondary reload is still needed if something
> > changed significantly, e.g.
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