On 8/27/24 18:10, Vineet Gupta wrote:
> On 8/7/24 10:47, Richard Sandiford wrote:
>> is probably not appropriate. We should probably just use the baseECC,
>> as suggested by the first sentence in the comment. It looks like the hack:
>>
>> diff --git a/gcc/haifa-sched.cc b/gcc/haifa-sched.cc
>> in
On 8/20/24 2:42 AM, Richard Sandiford wrote:
Vineet Gupta writes:
On 8/19/24 14:52, Richard Sandiford wrote:
2. On RISC-V sched1 is counter intuitively assuming HARD_FP is live due to the
weird interaction of DF infra (which always marks HARD_FP with
artificial def) and ira_no_alloc_regs.
Hi Richard,
On 8/7/24 10:47, Richard Sandiford wrote:
> I should probably start by saying that the "model" heuristic is now
> pretty old and was originally tuned for an in-order AArch32 core.
> The aim wasn't to *minimise* spilling, but to strike a better balance
> between parallelising with spill
Vineet Gupta writes:
> On 8/19/24 14:52, Richard Sandiford wrote:
>>> 2. On RISC-V sched1 is counter intuitively assuming HARD_FP is live due to
>>> the weird interaction of DF infra (which always marks HARD_FP with
>>> artificial def) and ira_no_alloc_regs.
>> In general, it isn't possible to pr
On 8/19/24 14:52, Richard Sandiford wrote:
>> 2. On RISC-V sched1 is counter intuitively assuming HARD_FP is live due to
>> the weird interaction of DF infra (which always marks HARD_FP with
>> artificial def) and ira_no_alloc_regs.
> In general, it isn't possible to predict at this stage whether
Vineet Gupta writes:
> On 8/6/24 17:36, Vineet Gupta wrote:
>> I'm currently pursuing a different trail which comes form observation
>> that initial model setup concludes that pressure is 28 so with 27
>> allocable regs we are bound to spill one.
>> More on that after I find something concrete.
>
On 8/6/24 17:36, Vineet Gupta wrote:
> I'm currently pursuing a different trail which comes form observation
> that initial model setup concludes that pressure is 28 so with 27
> allocable regs we are bound to spill one.
> More on that after I find something concrete.
(caveat: I enabled -fomit-fra
Vineet Gupta writes:
> On 8/7/24 12:28, Jeff Law wrote:
>> On 8/7/24 11:47 AM, Richard Sandiford wrote:
>>> I should probably start by saying that the "model" heuristic is now
>>> pretty old and was originally tuned for an in-order AArch32 core.
>>> The aim wasn't to *minimise* spilling, but to st
On Thu, Aug 8, 2024 at 12:17 AM Vineet Gupta wrote:
>
> On 8/7/24 12:28, Jeff Law wrote:
> > On 8/7/24 11:47 AM, Richard Sandiford wrote:
> >> I should probably start by saying that the "model" heuristic is now
> >> pretty old and was originally tuned for an in-order AArch32 core.
> >> The aim was
On 8/7/24 12:28, Jeff Law wrote:
> On 8/7/24 11:47 AM, Richard Sandiford wrote:
>> I should probably start by saying that the "model" heuristic is now
>> pretty old and was originally tuned for an in-order AArch32 core.
>> The aim wasn't to *minimise* spilling, but to strike a better balance
>> bet
On 8/7/24 11:47 AM, Richard Sandiford wrote:
I should probably start by saying that the "model" heuristic is now
pretty old and was originally tuned for an in-order AArch32 core.
The aim wasn't to *minimise* spilling, but to strike a better balance
between parallelising with spills vs. sequent
I should probably start by saying that the "model" heuristic is now
pretty old and was originally tuned for an in-order AArch32 core.
The aim wasn't to *minimise* spilling, but to strike a better balance
between parallelising with spills vs. sequentialising. At the time,
scheduling without taking
Hi Jeff
On 8/5/24 21:31, Jeff Law wrote:
> On 8/5/24 5:35 PM, Vineet Gupta wrote:
>> Hi Richard,
>>
>> I'm reaching out for some insight on PR/114729. Apologies in advance for
>> the long email.
>>
>> On RISC-V we are hitting sched1 pathology on SPEC2017 Cactu where
>> codegen spills are overwhelm
On 8/5/24 5:35 PM, Vineet Gupta wrote:
Hi Richard,
I'm reaching out for some insight on PR/114729. Apologies in advance for
the long email.
On RISC-V we are hitting sched1 pathology on SPEC2017 Cactu where
codegen spills are overwhelming the execution: disabling sched1 shaves
off 1.3 trillio
Hi Richard,
I'm reaching out for some insight on PR/114729. Apologies in advance for
the long email.
On RISC-V we are hitting sched1 pathology on SPEC2017 Cactu where
codegen spills are overwhelming the execution: disabling sched1 shaves
off 1.3 trillion dynamic icounts which is about half of tot
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