ome
target?
Joshua
--
发件人：juzhe.zh...@rivai.ai
发送时间：2023年12月22日(星期五) 18:32
收件人："cooper.joshua";
"gcc-patches"
抄 送：Jim Wilson; palmer;
andrew; "philipp.tomsich";
jeffreyalaw;
"christoph.muellner";
jinma; "cooper.qu&
On 12/22/23 01:07, juzhe.zh...@rivai.ai wrote:
You mean theadvector doesn't want the current RVV1.0 register overlap
magic as follows ?
*
The destination EEW is smaller than the source EEW and the overlap
is in the lowest-numbered part of the source register group (e.g.,
when
h_operand" " rK")
(match_operand 5 "const_int_operand" " i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
"TARGET_XTHEADVECTOR"
"vmsbc.vvm\t%0,%1,%2,%3"
[(set_attr "type" &quo
You mean theadvector doesn't want the current RVV1.0 register overlap magic as
follows ?
The destination EEW is smaller than the source EEW and the overlap is in the
lowest-numbered part of the source register group (e.g., when LMUL=1, vnsrl.wi
v0, v0, 3 is legal, but a destination of v1 is not
