On Thu, Jul 14, 2022 at 7:32 AM Roger Sayle wrote:
>
>
> On Mon, Jul 11, 2022, H.J. Lu wrote:
> > On Sun, Jul 10, 2022 at 2:38 PM Roger Sayle
> > wrote:
> > > Hi HJ,
> > >
> > > I believe this should now be handled by the post-reload (CSE) pass.
> > > Consider the simple test case:
> > >
> > > _
On Mon, Jul 11, 2022, H.J. Lu wrote:
> On Sun, Jul 10, 2022 at 2:38 PM Roger Sayle
> wrote:
> > Hi HJ,
> >
> > I believe this should now be handled by the post-reload (CSE) pass.
> > Consider the simple test case:
> >
> > __int128 a, b, c;
> > void foo()
> > {
> > a = 0;
> > b = 0;
> > c
On Sun, Jul 10, 2022 at 8:36 PM Roger Sayle wrote:
>
>
> Hi Uros,
> Yes, I agree. I think it makes sense to have a single STV pass (after
> combine and before reload). Let's hear what HJ thinks, but I'm
> happy to investigate a follow-up patch that unifies the STV passes.
> But it'll be easier t
be found for
> TI mode (mostly).
You are probably right. If there are no regressions in GCC testsuite,
my original motivation is no longer valid.
Thanks.
> Cheers,
> Roger
> --
>
> > -Original Message-
> > From: H.J. Lu
> > Sent: 10 July 2022 20:15
>
> -Original Message-
> From: H.J. Lu
> Sent: 10 July 2022 20:15
> To: Roger Sayle
> Cc: Uros Bizjak ; GCC Patches
> Subject: Re: [x86_64 PATCH] Improved Scalar-To-Vector (STV) support for
> TImode to V1TImode.
>
> On Sun, Jul 10, 2022 at 11:36 AM Roger Sayle
>
;s thoughts.
The TImode STV pass is run before the CSE pass so that
instructions changed or generated by the STV pass can be CSEed.
> Cheers,
> Roger
> --
>
> > -Original Message-
> > From: Uros Bizjak
> > Sent: 10 July 2022 19:06
> > To: Roger Sayle
&
2 19:06
> To: Roger Sayle
> Cc: gcc-patches@gcc.gnu.org; H. J. Lu
> Subject: Re: [x86_64 PATCH] Improved Scalar-To-Vector (STV) support for
> TImode to V1TImode.
>
> On Sat, Jul 9, 2022 at 2:17 PM Roger Sayle
> wrote:
> >
> >
> > This patch upgrades x86_64
On Sat, Jul 9, 2022 at 2:17 PM Roger Sayle wrote:
>
>
> This patch upgrades x86_64's scalar-to-vector (STV) pass to more
> aggressively transform 128-bit scalar TImode operations into vector
> V1TImode operations performed on SSE registers. TImode functionality
> already exists in STV, but only f
