Re: [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

2025-07-16 Thread Umesh Kalappa
>>>I fixed various nits in the ChangeLog to make the pre-commit hooks happy and pushed this to the trunk. Thanks a lot Jeff for fixing the Changelog and .md misinformatted (we use VS Code or VI with tab 4 spaces). and also use git-fix-changelog.py and check_GNU_style.py formatting ,which still loo

Re: [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

2025-07-15 Thread Jeff Law
On 7/14/25 11:34 PM, Umesh Kalappa wrote: Updated the test for rv32 accordingly and no regress found for runs like "runtest --tool gcc --target_board='riscv-sim/-march=rv32gc_zba_zbb_zbc_zbs/-mabi=ilp32d/-mcmodel=medlow' riscv.exp" and "runtest --tool gcc --target_board='riscv-sim/-march=rv

Re: [PATCH v5] RISC-V: Mips P8700 Conditional Move Support.

2025-07-15 Thread Umesh Kalappa
Hi @Jeff Law and all, https://patchwork.sourceware.org/project/gcc/patch/20250715053410.557741-1-ukalappa.m...@gmail.com/ looks ok to us ,please let me any comments for your end , Thank you ~U On Tue, Jul 15, 2025 at 11:04 AM Umesh Kalappa wrote: > Updated the test for rv32 accordingly and