Re: [PATCH 0/6] RISC-V: frm state-machine improvements

2025-05-17 Thread Jeff Law
On 5/10/25 9:46 PM, Vineet Gupta wrote: Frankly I'm surprised we need FRM adjustments as much as we do, though presumably there's some builtin or somesuch that we need to twiddle FRM to implement and as a result if the builtin ever gets used it leads to FRM games. But it still seems high.

Re: [PATCH 0/6] RISC-V: frm state-machine improvements

2025-05-12 Thread Vineet Gupta
On 5/11/25 19:22, 钟居哲 wrote: > Hi, vineet. > > >> I have a feeling this has to do with following: > >> https://godbolt.org/z/Px9es7j1r > > I saw in there are 2 fsrm instruction inside the main loop in Clang generated > ASM which I think GCC is better. > > Correct me if I am wrong. Thanks. Yes you

Re: [PATCH 0/6] RISC-V: frm state-machine improvements

2025-05-11 Thread 钟居哲
Hi, vineet. >> I have a feeling this has to do with following: >> https://godbolt.org/z/Px9es7j1r I saw in there are 2 fsrm instruction inside the main loop in Clang generated ASM which I think GCC is better. Correct me if I am wrong. Thanks. juzhe.zh...@rivai.ai From: Vineet Gupta Date: 2

Re: [PATCH 0/6] RISC-V: frm state-machine improvements

2025-05-10 Thread Vineet Gupta
On 5/10/25 06:49, Jeff Law wrote: > On 5/9/25 2:27 PM, Vineet Gupta wrote: >> Hi, >> >> This came out of Rivos perf team reporting (shoutout to Siavash) that >> some of the SPEC2017 workloads had unnecessary FRM wiggles, when >> none were needed. The writes in particular could be expensive. >> >> I

Re: [PATCH 0/6] RISC-V: frm state-machine improvements

2025-05-10 Thread Jeff Law
On 5/9/25 2:27 PM, Vineet Gupta wrote: Hi, This came out of Rivos perf team reporting (shoutout to Siavash) that some of the SPEC2017 workloads had unnecessary FRM wiggles, when none were needed. The writes in particular could be expensive. I started with reduced test for PR/119164 from blen