On 2023-04-22 08:08 Jeff Law wrote:
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>On 3/23/23 19:53, Feng Wang wrote:
>> This patch optimize the combine processing for sext.b/h in rv64.
>> Please refer to the following test case,
>> int sextb32(int x)
>> { return (x << 24) >> 24; }
>>
>> The rtl expression is as follows,
>> (insn 6 3 7
On 3/23/23 19:53, Feng Wang wrote:
This patch optimize the combine processing for sext.b/h in rv64.
Please refer to the following test case,
[ ... ]
I've opened BZ109592 to track this problem.
jeff
On 3/23/23 19:53, Feng Wang wrote:
This patch optimize the combine processing for sext.b/h in rv64.
Please refer to the following test case,
int sextb32(int x)
{ return (x << 24) >> 24; }
The rtl expression is as follows,
(insn 6 3 7 2 (set (reg:SI 138)
(ashift:SI (subreg/s/u:SI (reg
On 3/26/23 19:32, Feng Wang wrote:
On 2023-03-26 02:18 Jeff Law wrote:
On 3/23/23 20:45, juzhe.zh...@rivai.ai wrote:
Sounds like you are looking at redundant extension problem in RISC-V port.
This is the issue I want to fix but I don't find the time to do that.
My first impression is tha
On 2023-03-26 02:18 Jeff Law wrote:
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>
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>On 3/23/23 20:45, juzhe.zh...@rivai.ai wrote:
>> Sounds like you are looking at redundant extension problem in RISC-V port.
>> This is the issue I want to fix but I don't find the time to do that.
>> My first impression is that we need to fix redundant ex
On 3/23/23 20:45, juzhe.zh...@rivai.ai wrote:
Sounds like you are looking at redundant extension problem in RISC-V port.
This is the issue I want to fix but I don't find the time to do that.
My first impression is that we need to fix redundant extension in "ree"
PASS.
I am not sure.
It's ac
Hi Juzhe,
Thank you for your reply, I'm really doing some optimization work right now.
I am very interested in the question you have raised, and I will take the time
to try to optimize it.
I hope I can communicate with you and learn from you more in the future.
Thanks.
