Cc: Kito.cheng ; Wang, Yanzhang
Subject: RE: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed
load/store
Thanks Juzhe, make sense, let me update it soon.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 4, 2023 4:40 PM
To: Li, Pan2 ; gcc-patches
Cc: Kito.cheng ; Li, Pan2 ; Wang
Thanks Juzhe, make sense, let me update it soon.
Pan
From: juzhe.zh...@rivai.ai
Sent: Thursday, May 4, 2023 4:40 PM
To: Li, Pan2 ; gcc-patches
Cc: Kito.cheng ; Li, Pan2 ; Wang,
Yanzhang
Subject: Re: [PATCH] RISC-V: Legitimise the const0_rtx for RVV indexed
load/store
vluxei32.v v1,(0
vluxei32.v v1,(0),v1 is not correct assembly.
Instead, it should be vluxei32.v v1,(zero),v1
You should change the assembly print: (%1) --> (%z1)
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-05-04 16:35
To: gcc-patches
CC: juzhe.zhong; kito.cheng; pan2.li; yanzhang.wang
Subject: [P
