LGTM
juzhe.zh...@rivai.ai
From: Palmer Dabbelt
Date: 2023-05-12 06:31
To: juzhe.zhong
CC: gcc-patches; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add v_uimm_operand
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zh...@rivai.ai wrote:
>>> ;; V has 32-bit unsigned immediates. This h
On Thu, 11 May 2023 15:00:48 PDT (-0700), juzhe.zh...@rivai.ai wrote:
;; V has 32-bit unsigned immediates. This happens to be the same constraint asIt
should be 5-bit unsigned immediates>> ; the csr_operand, but it's not CSR
related.
(define_predicate "v_uimm_operand"
(match_operand 0 "csr
