I think it's harmless to let this patch in GCC-14.
So LGTM from my side to land this path in GCC-14..
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-26 01:07
To: Jeff Law; 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc
Subject: Re: [PATCH] RISC-V: Add initial cost handlin
> So where do we stand with this? Juzhe asked it to be rebased, but I
> don't see a rebased version in my inbox and I don't see anything that
> looks like this on the trunk.
I missed this one and figured as we're pretty late in the cycle it can
wait until GCC 15. Therefore let's call it "deferre
On 3/1/24 8:07 AM, Robin Dapp wrote:
+ /* Segment load/store permute cost. */
+ const int segment_permute_2;
+ const int segment_permute_4;
+ const int segment_permute_8;
Why do we only have 2/4/8, I think we should have 2/3/4/5/6/7/8
No idea why I posted that (wrong) version, I used i
Could you rebase to the trunk ? I don't think segment load store cost depends
on previous patch you sent.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2024-03-01 23:07
To: 钟居哲; gcc-patches; palmer; kito.cheng
CC: rdapp.gcc; Jeff Law
Subject: Re: [PATCH] RISC-V: Add initial cost handlin
> + /* Segment load/store permute cost. */
> + const int segment_permute_2;
> + const int segment_permute_4;
> + const int segment_permute_8;
>
> Why do we only have 2/4/8, I think we should have 2/3/4/5/6/7/8
No idea why I posted that (wrong) version, I used it for
some testing locally. At
-patches; palmer; kito.cheng
CC: rdapp.gcc; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Add initial cost handling for segment loads/stores.
> This patch looks odd to me.
> I don't see memrefs in the trunk code.
It's on top of the vle/vse offset handling patch from
a while bac
> This patch looks odd to me.
> I don't see memrefs in the trunk code.
It's on top of the vle/vse offset handling patch from
a while back that I haven't committed yet.
> Also, I prefer list all cost in cost tune info for NF = 2 ~ 8 like ARM SVE
> does:
I don't mind having separate costs for each
This patch looks odd to me.
I don't see memrefs in the trunk code.
Also, I prefer list all cost in cost tune info for NF = 2 ~ 8 like ARM SVE does:
/* Detect cases in which a vector load or store represents an
LD[234] or ST[234] instruction. */
switch (aarch64_ld234_st234_vectors (ki
