> Thanks for looking into the 64-bit failures, and actually if you want
> I can work on fixing them myself this afternoon.
Yes, you probably have a better grasp on the code than me.
--
Eric Botcazou
From: Eric Botcazou
Date: Wed, 9 Nov 2011 17:41:36 +0100
> There isn't an equivalent for 32-bit, is it? That is, you can load 8, 16 and
> 64 bits in the upper FP regs, but not 32 bits?
Indeed, you need to use normal 32-bit loads and thus the lower 32
float regs.
BTW, I suspect the paradoxical
> Eric, the testsuite target tests for vis2 and vi3 capable hardware
> work well in my own testing but if you find some problem with how
> it's done just let me know and I'll try to fix it up.
There are many failures in 64-bit mode with VIS1 because of the use of the high
part to expand vec_init,
From: Richard Henderson
Date: Sun, 06 Nov 2011 09:55:17 -0800
> On 11/05/2011 07:39 PM, David Miller wrote:
>> Richard, is there a better way to represent this in RTL? These
>> instructions basically load a single byte or half-word into the bottom
>> of a 64-bit float register, and clear the res
On 11/05/2011 07:39 PM, David Miller wrote:
> Richard, is there a better way to represent this in RTL? These
> instructions basically load a single byte or half-word into the bottom
> of a 64-bit float register, and clear the rest of that register with
> zeros. So the v4hi one is essentially load
