..@embecosm.com
> Subject: Re: [PATCH] [ARC] Add support for atomic memory built-in.
>
>
>
> On 07/12/15 13:25, Claudiu Zissulescu wrote:
> >
> > Tested with dg.exp (when passing -matomic to gcc compiler line, the
> atomic tests are also successfully executed).
>
I will add this text before "*memory_barrier" pattern:
;; For ARCHS, we use a hardware data memory barrier that waits for
;; completion of current data memory operations before initiating
;; similar data memory operations.
Once done, I will commit it.
Thanks,
Claudiu
>
> Tested with dg.exp (wh
On 07/12/15 13:25, Claudiu Zissulescu wrote:
Tested with dg.exp (when passing -matomic to gcc compiler line, the atomic
tests are also successfully executed).
The comment before "*memory_barrier" could use some elaboration on what
it does for TARGET_HS.
Otherwise, this is OK.
Hi,
> AFAICT, you use hardware synchronisation instruction for EMMODEL_SEQ,
> and compiler memory barriers for all other memory models (except
> MEMMODEL_RELAXED). That makes no sense; either the platform needs
> explicit instructions for memory coherency, or it doesn't.
Indeed, we on purpose mi
On 16/11/15 10:18, Claudiu Zissulescu wrote:
+/* Expand code to perform a 8 or 16-bit compare and swap by doing
+ 32-bit compare and swap on the word containing the byte or
+ half-word. The difference between a weak and a strong CAS is that
+ the weak version may simply fail. The stro
Ping. This patch is stalling for two weeks.
Thanks,
Claudiu
On Mon, Nov 16, 2015 at 11:18 AM, Claudiu Zissulescu
wrote:
> This patch adds support for atomic memory built-in for ARCHS and ARC700.
> Tested with dg.exp.
>
> OK to apply?
>
> Thanks,
> Claudiu
>
> ChangeLogs:
> gcc/
>
> 2015-11-12
