On Wed, 28 Nov 2018, Andre Vieira (lists) wrote:
> Here are the documentation bits I forgot, I've also opened PR 88224 in
> bugzilla for this issue.
>
> Is this OK for trunk and gcc-8 backport?
>
> gcc/ChangeLog:
> 2018-11-28 Andre Vieira
>
> PR target/88224
> * config/arm/ar
On 28/11/18 10:57, Richard Earnshaw (lists) wrote:
> On 28/11/2018 10:43, Andre Vieira (lists) wrote:
>> On 27/11/18 14:18, Richard Earnshaw (lists) wrote:
>>> On 27/11/2018 14:10, Andre Vieira (lists) wrote:
Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both
On 28/11/2018 10:43, Andre Vieira (lists) wrote:
> On 27/11/18 14:18, Richard Earnshaw (lists) wrote:
>> On 27/11/2018 14:10, Andre Vieira (lists) wrote:
>>>
>>> Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both
>>> have
>>> SP only and SP + DP configurations.
>>
>> You're
On 27/11/18 14:18, Richard Earnshaw (lists) wrote:
> On 27/11/2018 14:10, Andre Vieira (lists) wrote:
>>
>> Both Cortex-R7 and Cortex-R8 support FP16 conversion instructions and both
>> have
>> SP only and SP + DP configurations.
>
> You're missing the updates to the documentation.
>
> R.
>
Oop
On 27/11/2018 14:10, Andre Vieira (lists) wrote:
>
> Hi,
>
> This patch fixes the FPU configurations of Cortex-R7 and Cortex-R8,
> enabling the use of FP16 conversion instructions for both and adding the
> option to disable double precision instruction support using '+nofp.dp'.
>
> Passes the se
