On Tue, Sep 26, 2017 at 10:50:14AM -0400, Michael Meissner wrote:
> * gcc.target/powerpc/pr71977-1.c: Update test to know that we
> don't generate a 32-bit shift after doing XSCVDPSPN.
> * gcc.target/powerpc/direct-move-float1.c: Likewise.
> * gcc.target/powerpc/direct-move-
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
