On Tue, Sep 26, 2017 at 06:37:17PM -0400, Michael Meissner wrote:
> On Tue, Sep 26, 2017 at 04:56:54PM -0500, Segher Boessenkool wrote:
> > On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> > > * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> > > Adjust code
On Tue, Sep 26, 2017 at 04:56:54PM -0500, Segher Boessenkool wrote:
> On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> > * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> > Adjust code to eliminate needing to do the shift right 32-bits
> > operation a
On Tue, Sep 26, 2017 at 10:48:29AM -0400, Michael Meissner wrote:
> * config/rs6000/vsx.md (peephole for optimizing move SF to GPR):
> Adjust code to eliminate needing to do the shift right 32-bits
> operation after XSCVDPSPN.
After staring at this way too long... Looks correct.
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
