Hi!
On Tue, Sep 26, 2017 at 10:30:03AM -0400, Michael Meissner wrote:
> I have broken the patches down to 8 chunks.
Thanks for doing this.
> +(define_split
> + [(set (match_operand:DI 0 "int_reg_operand")
> + (sign_extend:DI (match_operand:SI 1 "vsx_register_operand")))]
Should be EXTSI in
Off list, Segher asked that I break the patch eliminating a shift right when
transfering SFmode from a vector register to a GPR register down into smaller
chunks. The power7 and power8 instructions that convert values in the double
precision format to single precision actually duplicate the 32-bit
