Re: RISC-V frm mode switching and late_combine2

2025-06-05 Thread Richard Sandiford
Jeff Law writes: > On 6/3/25 11:11 AM, Richard Sandiford wrote: >> Vineet Gupta writes: >>> On 6/3/25 08:24, Richard Sandiford wrote: I think the issue is that: (insn 9 8 27 2 (parallel [ (asm_operands/v ("fsrm %0") ("") 0 [ (reg:SI 15 a5

Re: RISC-V frm mode switching and late_combine2

2025-06-04 Thread Jeff Law
On 6/3/25 11:11 AM, Richard Sandiford wrote: Vineet Gupta writes: On 6/3/25 08:24, Richard Sandiford wrote: I think the issue is that: (insn 9 8 27 2 (parallel [ (asm_operands/v ("fsrm %0") ("") 0 [ (reg:SI 15 a5 [139]) ]

Re: RISC-V frm mode switching and late_combine2

2025-06-04 Thread Vineet Gupta
On 6/4/25 04:45, Richard Sandiford wrote: > I think the issue is that: > > (insn 9 8 27 2 (parallel [ > (asm_operands/v ("fsrm %0") ("") 0 [ > (reg:SI 15 a5 [139]) > ] > [ > (asm_inp

Re: RISC-V frm mode switching and late_combine2

2025-06-04 Thread Richard Sandiford
Vineet Gupta writes: > On 6/3/25 10:11, Richard Sandiford wrote: >> Vineet Gupta writes: >>> On 6/3/25 08:24, Richard Sandiford wrote: I think the issue is that: (insn 9 8 27 2 (parallel [ (asm_operands/v ("fsrm %0") ("") 0 [ (reg:SI 15 a5

Re: RISC-V frm mode switching and late_combine2

2025-06-03 Thread Vineet Gupta
On 6/3/25 10:11, Richard Sandiford wrote: > Vineet Gupta writes: >> On 6/3/25 08:24, Richard Sandiford wrote: >>> I think the issue is that: >>> >>> (insn 9 8 27 2 (parallel [ >>> (asm_operands/v ("fsrm %0") ("") 0 [ >>> (reg:SI 15 a5 [139]) >>> ]

Re: RISC-V frm mode switching and late_combine2

2025-06-03 Thread Richard Sandiford
Vineet Gupta writes: > On 6/3/25 08:24, Richard Sandiford wrote: >> I think the issue is that: >> >> (insn 9 8 27 2 (parallel [ >> (asm_operands/v ("fsrm %0") ("") 0 [ >> (reg:SI 15 a5 [139]) >> ] >> [ >> (asm_inp

Re: RISC-V frm mode switching and late_combine2

2025-06-03 Thread Vineet Gupta
On 6/3/25 08:24, Richard Sandiford wrote: > I think the issue is that: > > (insn 9 8 27 2 (parallel [ > (asm_operands/v ("fsrm %0") ("") 0 [ > (reg:SI 15 a5 [139]) > ] > [ > (asm_input:SI ("r") frm-run-1.c:33) >

Re: RISC-V frm mode switching and late_combine2

2025-06-03 Thread Richard Sandiford
Vineet Gupta writes: >> ...is from late-combine2, so after RA has completed, whereas the earlier >> dump is from mode switching, so it's hard to tell what late-combine2 is >> operating on. Could you give the RTL as late-combine2 sees it? >> (That would normally be the result of pass_postreload_cs

Re: RISC-V frm mode switching and late_combine2

2025-06-02 Thread Vineet Gupta
Hi Richard, On 6/2/25 01:27, Richard Sandiford wrote: > Vineet Gupta writes: >> +CC gcc-patches >> >> On 5/30/25 14:04, Vineet Gupta wrote: >>> Hi Jeff, Richard >>> >>> As part of RISC-V FRM mode switching improvements, I'm running into a >>> behavior >>> in late_combine2 where it is eliminating

Re: RISC-V frm mode switching and late_combine2

2025-06-02 Thread Richard Sandiford
Vineet Gupta writes: > +CC gcc-patches > > On 5/30/25 14:04, Vineet Gupta wrote: >> Hi Jeff, Richard >> >> As part of RISC-V FRM mode switching improvements, I'm running into a >> behavior >> in late_combine2 where it is eliminating FRM save/restores when it is >> desired to >> keep them. >> >>

Re: RISC-V frm mode switching and late_combine2

2025-05-30 Thread Vineet Gupta
+CC gcc-patches On 5/30/25 14:04, Vineet Gupta wrote: > Hi Jeff, Richard > > As part of RISC-V FRM mode switching improvements, I'm running into a behavior > in late_combine2 where it is eliminating FRM save/restores when it is desired > to > keep them. > > I'm pasting snippet of RTL dumps, could