Re: RISC-V: Replace unspec with bitreverse in riscv_brev8_ insn

2023-07-26 Thread Jeff Law via Gcc-patches
On 7/26/23 02:21, Kito Cheng via Gcc-patches wrote: My understanding is the semantic is slightly different, brev8 is only the bit reverse within each byte, but bitreverse means did bit reverse for the whole content of the mode, e.g. riscv_brev8_si will bit reserved within 32 bit. Using RV32 a

Re: RISC-V: Replace unspec with bitreverse in riscv_brev8_ insn

2023-07-26 Thread Kito Cheng via Gcc-patches
My understanding is the semantic is slightly different, brev8 is only the bit reverse within each byte, but bitreverse means did bit reverse for the whole content of the mode, e.g. riscv_brev8_si will bit reserved within 32 bit. Using RV32 as example: UNSPEC_BREV8: rd[0...7] = rs[7...0] rd[8...15

RISC-V: Replace unspec with bitreverse in riscv_brev8_ insn

2023-07-26 Thread Jivan Hakobyan via Gcc-patches
This small patch replaces unspec opcode with bitreverse in riscv_brev8_ insn. gcc/ChangeLog: * config/riscv/crypto.md (UNSPEC_BREV8): Remov. (riscv_brev8_): Use bitreverse opcode. -- With the best regards Jivan Hakobyan diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/