Here is version 3 of my patch to implement the SIMD ABI on Aarch64.
I am having a problem with how to handle a SIMD function calling a
non-SIMD function. When this happens the SIMD function needs to save
V8 to V23 because it cannot count on the non-SIMD function to save
all 128 bits of these regis
Here is an updated version of my patch for the Aarch64 SIMD ABI. I
think the writeback register saves are correct now and I improved the
register allocation by defining REG_ALLOC_ORDER. I also added clobbers
to expand_call when calling a non-SIMD function from a SIMD function.
I am still testing
Steve Ellcey wrote:
> OK, I think I understand this a bit better now. I think my main
> problem is with the term 'writeback' which I am not used to seeing.
> But if I understand things correctly we are saving one or two registers
> and (possibly) updating the stack pointer using auto-increment/a
On Fri, 2018-07-20 at 11:11 +, Wilco Dijkstra wrote:
> Steve Ellcey wrote:
>
> > Yes, I see where I missed this in aarch64_push_regs
> > and aarch64_pop_regs. I think that is why the second of
> > Wilco's two examples (f2) is wrong. I am unclear about
> > exactly what is meant by writeback
Steve Ellcey wrote:
> Yes, I see where I missed this in aarch64_push_regs
> and aarch64_pop_regs. I think that is why the second of
> Wilco's two examples (f2) is wrong. I am unclear about
> exactly what is meant by writeback and why we have it and
> how that and callee_adjust are used. Any cha
On Thu, 2018-07-19 at 08:31 +0100, Richard Sandiford wrote:
>
> > @@ -4706,8 +4730,11 @@ aarch64_process_components (sbitmap
> > components, bool prologue_p)
> > while (regno != last_regno)
> > {
> > /* AAPCS64 section 5.1.2 requires only the bottom 64 bits to be saved
> > - so
Hi Steve,
> This patch checks for SIMD functions and saves the extra registers when
> needed. It does not change the caller behavour, so with just this patch
> there may be values saved by both the caller and callee. This is not
> efficient, but it is correct code.
I tried a few simple test cas
On Thu, Jul 19, 2018 at 8:31 AM, Richard Sandiford
wrote:
> Hi,
>
> Thanks for doing this.
>
> Steve Ellcey writes:
>> This is a patch to support the Aarch64 SIMD ABI [1] in GCC. I intend
>> to eventually follow this up with two more patches; one to define the
>> TARGET_SIMD_CLONE* macros and on
Hi,
Thanks for doing this.
Steve Ellcey writes:
> This is a patch to support the Aarch64 SIMD ABI [1] in GCC. I intend
> to eventually follow this up with two more patches; one to define the
> TARGET_SIMD_CLONE* macros and one to improve the GCC register
> allocation/usage when calling SIMD fun
This is a patch to support the Aarch64 SIMD ABI [1] in GCC. I intend
to eventually follow this up with two more patches; one to define the
TARGET_SIMD_CLONE* macros and one to improve the GCC register
allocation/usage when calling SIMD functions.
The significant difference between the standard AR
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