On Mon, May 21, 2012 at 9:33 AM, H.J. Lu wrote:
> On Wed, Apr 11, 2012 at 7:35 AM, Bernd Schmidt
> wrote:
>> On 12/23/2011 05:31 PM, Vladimir Makarov wrote:
>>> On 12/21/2011 09:09 AM, Bernd Schmidt wrote:
This patch was an experiment to see if we can get the same improvement
with modi
On Wed, Apr 11, 2012 at 7:35 AM, Bernd Schmidt wrote:
> On 12/23/2011 05:31 PM, Vladimir Makarov wrote:
>> On 12/21/2011 09:09 AM, Bernd Schmidt wrote:
>>> This patch was an experiment to see if we can get the same improvement
>>> with modifications to IRA, making it more tolerant to over-aggressi
On 04/11/2012 10:35 AM, Bernd Schmidt wrote:
On 12/23/2011 05:31 PM, Vladimir Makarov wrote:
On 12/21/2011 09:09 AM, Bernd Schmidt wrote:
This patch was an experiment to see if we can get the same improvement
with modifications to IRA, making it more tolerant to over-aggressive
scheduling. THe
On 12/23/2011 05:31 PM, Vladimir Makarov wrote:
> On 12/21/2011 09:09 AM, Bernd Schmidt wrote:
>> This patch was an experiment to see if we can get the same improvement
>> with modifications to IRA, making it more tolerant to over-aggressive
>> scheduling. THe idea is that if an instruction sets a
On 12/21/2011 09:09 AM, Bernd Schmidt wrote:
For a customer I've looked into improving code for 456.hmmer on a mips64
target. The benchmark responds to -fsched-pressure, which reduces
lifetimes of a few registers.
This patch was an experiment to see if we can get the same improvement
with modifi
For a customer I've looked into improving code for 456.hmmer on a mips64
target. The benchmark responds to -fsched-pressure, which reduces
lifetimes of a few registers.
This patch was an experiment to see if we can get the same improvement
with modifications to IRA, making it more tolerant to over
