nd ext in further improvements.
Pan
-Original Message-
From: Jeff Law
Sent: Monday, September 2, 2024 11:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com
Subject: Re: [PATCH v1] RISC-V: Support form 1 of integer scalar .SAT_A
Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com
Subject: Re: [PATCH v1] RISC-V: Support form 1 of integer scalar .SAT_ADD
On 8/29/24 12:25 AM, pan2...@intel.com wrote:
From: Pan Li
This patch would like to support the scalar signed ssadd pattern
for the RISC-V
zhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp....@gmail.com
Subject: Re: [PATCH v1] RISC-V: Support form 1 of integer scalar .SAT_ADD
On 8/29/24 12:25 AM, pan2...@intel.com wrote:
> From: Pan Li
>
> This patch would like to support the scalar signed ssadd pattern
> for the RISC-V
On 8/29/24 12:25 AM, pan2...@intel.com wrote:
From: Pan Li
This patch would like to support the scalar signed ssadd pattern
for the RISC-V backend. Aka
Form 1:
#define DEF_SAT_S_ADD_FMT_1(T, UT, MIN, MAX) \
T __attribute__((noinline)) \
sat_s_add_##T##_fmt_1 (T x,
