RE: [PATCH v1] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD

2024-09-18 Thread Li, Pan2
rt future. Pan -Original Message- From: Jeff Law Sent: Wednesday, September 18, 2024 11:10 PM To: Li, Pan2 ; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com Subject: Re: [PATCH v1] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD

Re: [PATCH v1] RISC-V: Add testcases for form 2 of signed scalar SAT_ADD

2024-09-18 Thread Jeff Law
On 9/12/24 8:14 PM, pan2...@intel.com wrote: From: Pan Li This patch would like to add testcases of the signed scalar SAT_ADD for form 2. Aka: Form 2: #define DEF_SAT_S_ADD_FMT_2(T, UT, MIN, MAX) \ T __attribute__((noinline)) \ sat_s_add_##T##_fmt_2 (T x, T y)