-
> -Original Message-
> From: Jeff Law
> Sent: 14 March 2022 15:30
> To: Roger Sayle ; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] middle-end: Support ABIs that pass FP values as wider
> integers.
>
>
>
> On 2/9/2022 1:12 PM, Roger Sayle wrote:
> > Th
On 2/9/2022 1:12 PM, Roger Sayle wrote:
This patch adds middle-end support for target ABIs that pass/return
floating point values in integer registers with precision wider than
the original FP mode. An example, is the nvptx backend where 16-bit
HFmode registers are passed/returned as (promote
>> Anyway, I checked what cuda does for HF, and it passes a byte array:
>>> .param .align 2 .b8 _Z5helloPj6__halfs_param_1[2], ...
> >
> > The one precedent that I can point to is that LLVM's nvptx backend passes
> > HFmode values in SImode regs, see https://reviews.llvm.org/D28540
>
> Interes
ns of GCC, before handling of SUBREGs was tightened up,
so this might be considered a regression.
Cheers,
Roger
--
-Original Message-
From: Tom de Vries
Sent: 22 February 2022 15:43
To: Roger Sayle ; gcc-patches@gcc.gnu.org
Subject: Re: [PATCH] middle-end: Support ABIs that pass FP v
UBREGs was tightened up,
so this might be considered a regression.
Cheers,
Roger
--
> -Original Message-
> From: Tom de Vries
> Sent: 22 February 2022 15:43
> To: Roger Sayle ; gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH] middle-end: Support ABIs that pass FP values as w
On 2/9/22 21:12, Roger Sayle wrote:
This patch adds middle-end support for target ABIs that pass/return
floating point values in integer registers with precision wider than
the original FP mode. An example, is the nvptx backend where 16-bit
HFmode registers are passed/returned as (promoted to)
