r 30, 2013 1:54 AM
To: Richard Biener
Cc: Jan Hubicka; Gopalasubramanian, Ganesh; gcc-patches@gcc.gnu.org; Uros
Bizjak (ubiz...@gmail.com); H.J. Lu (hjl.to...@gmail.com)
Subject: Re: Fix scheduler ix86_issue_rate and ix86_adjust_cost for modern x86
chips
> On Fri, 25 Oct 2013, Jan Hubick
> On Fri, 25 Oct 2013, Jan Hubicka wrote:
>
> > > > OK, so it is about 2%. Did you try if you need lookahead even in the
> > > > early pass (before reload)? My guess would be so, but if not, it could
> > > > cut the cost to half. For -Ofast/-O3 it looks resonable to me, but we
> > > > will
On Fri, 25 Oct 2013, Jan Hubicka wrote:
> > > OK, so it is about 2%. Did you try if you need lookahead even in the
> > > early pass (before reload)? My guess would be so, but if not, it could
> > > cut the cost to half. For -Ofast/-O3 it looks resonable to me, but we
> > > will need to anno
> > OK, so it is about 2%. Did you try if you need lookahead even in the early
> > pass (before reload)? My guess would be so, but if not, it could cut the
> > cost to half. For -Ofast/-O3 it looks resonable to me, but we will need
> > to announce it on the ML. For other settings I think we
day, October 24, 2013 6:48 PM
To: Gopalasubramanian, Ganesh
Cc: Jan Hubicka; gcc-patches@gcc.gnu.org; Uros Bizjak (ubiz...@gmail.com); H.J.
Lu (hjl.to...@gmail.com)
Subject: Re: Fix scheduler ix86_issue_rate and ix86_adjust_cost for modern x86
chips
> Hi,
>
> > Is this with -fschedule-
2:54 PM
> To: Gopalasubramanian, Ganesh
> Cc: gcc-patches@gcc.gnu.org; Uros Bizjak (ubiz...@gmail.com); hubi...@ucw.cz;
> H.J. Lu (hjl.to...@gmail.com)
> Subject: Re: Fix scheduler ix86_issue_rate and ix86_adjust_cost for modern
> x86 chips
>
> > Attached is the patch which doe
[mailto:hubi...@ucw.cz]
Sent: Thursday, October 24, 2013 2:54 PM
To: Gopalasubramanian, Ganesh
Cc: gcc-patches@gcc.gnu.org; Uros Bizjak (ubiz...@gmail.com); hubi...@ucw.cz;
H.J. Lu (hjl.to...@gmail.com)
Subject: Re: Fix scheduler ix86_issue_rate and ix86_adjust_cost for modern x86
chips
> At
> Attached is the patch which does the following scheduler related changes.
> * re-models bdver3 decoder.
> * It enables lookahead with value 8 for all BD architectures. The patch
> doesn't consider if reloading is completed or not (an area that needs to be
> worked on).
> * The issue rate for BD
Attached is the patch which does the following scheduler related changes.
* re-models bdver3 decoder.
* It enables lookahead with value 8 for all BD architectures. The patch doesn't
consider if reloading is completed or not (an area that needs to be worked on).
* The issue rate for BD architecture
be however simply because the model is broken. Also SPEC is not the best
benchmark for scheduling, since it has many other bounds.
>
> > I will work on replacing most of the CPU cases into tuning flags + costs.
> I am planning to get bdver4 enablement in place once scheduler descript
est
benchmark for scheduling, since it has many other bounds.
>
> > I will work on replacing most of the CPU cases into tuning flags + costs.
> I am planning to get bdver4 enablement in place once scheduler descriptions
> for bdver3 is done with.
> I will have cycles to look in
-
From: Jan Hubicka [mailto:hubi...@ucw.cz]
Sent: Tuesday, October 08, 2013 3:20 PM
To: Gopalasubramanian, Ganesh
Cc: Jan Hubicka; gcc-patches@gcc.gnu.org; hjl.to...@gmail.com
Subject: Re: Fix scheduler ix86_issue_rate and ix86_adjust_cost for modern x86
chips
> Hi Honza,
>
> I am planning to upda
> Hi Honza,
>
> I am planning to update the scheduler descriptions for bdver3 first.
> Attached is the patch. Please let me know your comments if any.
>
> Though I agree on merging bdver1/2 and bdver3 on most parts, the FP lines and
> decoding schemes are different. So, let me know how can I app
these.
Regards
Ganesh
-Original Message-
From: Jan Hubicka [mailto:hubi...@ucw.cz]
Sent: Monday, September 30, 2013 4:47 PM
To: gcc-patches@gcc.gnu.org; Gopalasubramanian, Ganesh; hjl.to...@gmail.com
Subject: Fix scheduler ix86_issue_rate and ix86_adjust_cost for modern x86 chips
Hi
Hi,
while looking into schedules produced for Buldozer and Core I noticed that they
do not seem to match reality. This is because ix86_issue_rate limits those CPUs
into 3 instructions per cycle, while they are designed to do 4 and somewhat
confused ix86_adjust_cost.
I also added stack engine int
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