回复:回复:[PATCH v3 0/6] RISC-V: Support XTheadVector extension

2023-12-22 Thread joshua
gt;; palmer <mailto:pal...@dabbelt.com >; andrew <mailto:and...@sifive.com >; philipp.tomsich <mailto:philipp.toms...@vrull.eu >; jeffreyalaw <mailto:jeffreya...@gmail.com >; christoph.muellner <mailto:christoph.muell...@vrull.eu >; jinma <mailto:ji...@linux.alibaba.co

回复:回复:[PATCH v3 0/6] RISC-V: Support XTheadVector extension

2023-12-22 Thread joshua
Hi Juzhe, What xtheadvector needs to handle is just that destination vector register cannot overlap source vector register group for instructions like vmadc/vmsbc. That is not what group_overlap means. We nned to add "&" to the registers in the corresponding xtheadvector patterns while rvv 1.0 d