On Tue, 14 Dec 2021, Prathamesh Kulkarni wrote:
> On Tue, 7 Dec 2021 at 19:08, Richard Sandiford
> wrote:
> >
> > Prathamesh Kulkarni writes:
> > > On Thu, 2 Dec 2021 at 23:11, Richard Sandiford
> > > wrote:
> > >>
> > >> Prathamesh Kulkarni writes:
> > >> > Hi Richard,
> > >> > I have attache
On Tue, 7 Dec 2021 at 19:08, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > On Thu, 2 Dec 2021 at 23:11, Richard Sandiford
> > wrote:
> >>
> >> Prathamesh Kulkarni writes:
> >> > Hi Richard,
> >> > I have attached a WIP untested patch for PR96463.
> >> > IIUC, the PR suggests to t
Prathamesh Kulkarni writes:
> On Thu, 2 Dec 2021 at 23:11, Richard Sandiford
> wrote:
>>
>> Prathamesh Kulkarni writes:
>> > Hi Richard,
>> > I have attached a WIP untested patch for PR96463.
>> > IIUC, the PR suggests to transform
>> > lhs = svld1rq ({-1, -1, ...}, &v[0])
>> > into:
>> > lhs =
On Thu, 2 Dec 2021 at 23:11, Richard Sandiford
wrote:
>
> Prathamesh Kulkarni writes:
> > Hi Richard,
> > I have attached a WIP untested patch for PR96463.
> > IIUC, the PR suggests to transform
> > lhs = svld1rq ({-1, -1, ...}, &v[0])
> > into:
> > lhs = vec_perm_expr
> > if v is vector of 4 ele
Prathamesh Kulkarni writes:
> Hi Richard,
> I have attached a WIP untested patch for PR96463.
> IIUC, the PR suggests to transform
> lhs = svld1rq ({-1, -1, ...}, &v[0])
> into:
> lhs = vec_perm_expr
> if v is vector of 4 elements, and each element is 32 bits on little
> endian target ?
>
> I am s
Hi Richard,
I have attached a WIP untested patch for PR96463.
IIUC, the PR suggests to transform
lhs = svld1rq ({-1, -1, ...}, &v[0])
into:
lhs = vec_perm_expr
if v is vector of 4 elements, and each element is 32 bits on little
endian target ?
I am sorry if this sounds like a silly question, but I
