From: Eric Botcazou
Date: Mon, 15 Apr 2013 18:07:05 +0200
>> We can actually support this by adding patterns for the partial store
>> instructions, which can store 8-bit and 16-bit quantities from FP
>> registers.
>
> Ah, indeed, with -mvis. Not clear whether that would really be worthwhile.
W
> No objections.
Thanks.
> We can actually support this by adding patterns for the partial store
> instructions, which can store 8-bit and 16-bit quantities from FP
> registers.
Ah, indeed, with -mvis. Not clear whether that would really be worthwhile.
--
Eric Botcazou
From: Eric Botcazou
Date: Sun, 14 Apr 2013 10:39:59 +0200
> To my great surprise, this PR shows that the SPARC back-end allows QImode and
> HImode values to live in FP registers, but can neither load nor move them.
> This can result in an unrecognizable move insn between FP registers or an
> il
To my great surprise, this PR shows that the SPARC back-end allows QImode and
HImode values to live in FP registers, but can neither load nor move them.
This can result in an unrecognizable move insn between FP registers or an
illegal fdtox instruction in 64-bit mode as shown by the submitted tes
