Committed on trunk with typo fixed, thanks!
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f0cd40f71ba424bde94dcddbf1df67bb100b82ef
Jiawei
在 2025/6/4 21:33, Jeff Law 写道:
On 6/4/25 3:56 AM, Jiawei wrote:
This patch adds support for the XiangShan Kunminghu CPU in GCC, allowing
the use of the `-
On 6/4/25 3:56 AM, Jiawei wrote:
This patch adds support for the XiangShan Kunminghu CPU in GCC, allowing
the use of the `-mcpu=xiangshan-kunminghu` option.
XiangShan-KunMingHu is the third-generation open-source high-performance
RISC-V processor.[1] You can find the corresponding ISA extensi
On Wed, 2025-06-04 at 17:56 +0800, Jiawei wrote:
> +RISCV_CORE("xiangshan-kunminghu",
> "rv64imafdcbvh_sdtrig_sha_shcounterenw_"
> +
> "shgatpa_shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd_"
> +
> "smaia_smcsrind_smdbltrp_smmpm_smnpm_smrnmi
> On 4 Jun 2025, at 18:20, Xi Ruoyao wrote:
>
> On Wed, 2025-06-04 at 17:56 +0800, Jiawei wrote:
>> +RISCV_CORE("xiangshan-kunminghu",
>> "rv64imafdcbvh_sdtrig_sha_shcounterenw_"
>> +
>> "shgatpa_shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd_"
>> +
>> "smaia_smcsrind_smdbltrp
This patch adds support for the XiangShan Kunminghu CPU in GCC, allowing
the use of the `-mcpu=xiangshan-kunminghu` option.
XiangShan-KunMingHu is the third-generation open-source high-performance
RISC-V processor.[1] You can find the corresponding ISA extension from the
XiangShan Github repositor
