On 10/29/2014 03:37 AM, Zhenqiang Chen wrote:
> It's my fault. %m/%M work well in the new patch.
>
> And I add a check
>
> aarch64_ccmp_mode_to_code (GET_MODE (operands[1])) == GET_CODE (operands[5])
>
> on the patterns to make sure that the compare and CC mode are aligned.
Looks good.
r~
> -Original Message-
> From: gcc-patches-ow...@gcc.gnu.org [mailto:gcc-patches-
> ow...@gcc.gnu.org] On Behalf Of Richard Henderson
> Sent: Monday, October 27, 2014 11:47 PM
> To: Zhenqiang Chen
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [Ping] [PATCH, 8/10] aarch6
On 10/27/2014 12:49 AM, Zhenqiang Chen wrote:
> + {AARCH64_CC_Z, 0}, /* EQ, Z == 1. */
> + {0, AARCH64_CC_Z}, /* NE, Z == 0. */
> + {AARCH64_CC_C, 0}, /* CS, C == 1. */
> + {0, AARCH64_CC_C}, /* CC, C == 0. */
> + {0, 0}, /* MI, not supported*/
> + {0, 0}, /* PL, not supported*/
> + {0,
> -Original Message-
> From: Richard Henderson [mailto:r...@redhat.com]
> Sent: Sunday, October 12, 2014 4:12 AM
> To: Zhenqiang Chen; gcc-patches@gcc.gnu.org
> Subject: Re: [Ping] [PATCH, 8/10] aarch64: ccmp insn patterns
>
> On 09/22/2014 11:45 PM,
On 09/22/2014 11:45 PM, Zhenqiang Chen wrote:
> +(define_expand "cbranchcc4"
> + [(set (pc) (if_then_else
> + (match_operator 0 "aarch64_comparison_operator"
> +[(match_operand 1 "cc_register" "")
> + (const_int 0)])
> + (label_ref (match_operand 3 "" ""
Ping?
Patch is attached for easy to apply.
Move the cstorecc4 pattern from "[PATCH, 10/10] aarch64: Handle ccmp in
ifcvt to make it work with cmov" to this patch, since cmov optimization does
not depend on that patch.
Thanks!
-Zhenqiang
ChangeLog:
2014-09-23 Zhenqiang Chen
* config/
