On Fri, Mar 22, 2019 at 05:35:02PM +, James Greenhalgh wrote:
> On Mon, Mar 11, 2019 at 04:10:15PM +, Steve Ellcey wrote:
> > Richard,
> >
> > I don't necessarily disagree with anything in your comments and long
> > term I think that is the right direction, but I wonder if that level of
>
On Mon, Mar 11, 2019 at 04:10:15PM +, Steve Ellcey wrote:
> Richard,
>
> I don't necessarily disagree with anything in your comments and long
> term I think that is the right direction, but I wonder if that level of
> change is appropriate for GCC Stage 4 which is where we are now. Your
> cha
Richard,
I don't necessarily disagree with anything in your comments and long
term I think that is the right direction, but I wonder if that level of
change is appropriate for GCC Stage 4 which is where we are now. Your
changes would require fixes in shared code, whereas setting
REG_ALLOC_ORDER o
Steve Ellcey writes:
> This is a patch to fix the register allocation in SIMD functions. In
> normal functions registers V16 to V31 are all caller saved. In SIMD
> functions V16 to V23 are callee saved and V24 to V31 are caller saved.
> This means that SIMD functions should use V24 to V31 before
This is a patch to fix the register allocation in SIMD functions. In
normal functions registers V16 to V31 are all caller saved. In SIMD
functions V16 to V23 are callee saved and V24 to V31 are caller saved.
This means that SIMD functions should use V24 to V31 before V16 to V23
in order to avoid
