RE: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence

l.com>>; gcc-patches mailto:gcc-patches@gcc.gnu.org>> Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2 mailto:pan2...@intel.com>>; Wang, Yanzhang mailto:yanzhang.w...@intel.com>> Subject: Re: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequenc

RE: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence

.wang<mailto:yanzhang.w...@intel.com> Subject: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence From: Pan Li mailto:pan2...@intel.com>> This patch would like to optimize the VLS vector initialization like repeating sequence. From the vslide1down to the vmerge with

Re: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence

; kito.cheng; pan2.li; yanzhang.wang Subject: [PATCH v6] RISC-V: Using merge approach to optimize repeating sequence From: Pan Li This patch would like to optimize the VLS vector initialization like repeating sequence. From the vslide1down to the vmerge with a simple cost model, aka every instruction

[PATCH v6] RISC-V: Using merge approach to optimize repeating sequence

From: Pan Li This patch would like to optimize the VLS vector initialization like repeating sequence. From the vslide1down to the vmerge with a simple cost model, aka every instruction only has 1 cost. Given code with -march=rv64gcv_zvl256b --param riscv-autovec-preference=fixed-vlmax typedef i