Committed with more comments, thanks Robin.
Pan
-Original Message-
From: Robin Dapp
Sent: Saturday, May 18, 2024 3:32 AM
To: Li, Pan2 ; gcc-patches@gcc.gnu.org
Cc: rdapp@gmail.com; juzhe.zh...@rivai.ai; kito.ch...@gmail.com
Subject: Re: [PATCH v6] RISC-V: Implement IFN SAT_ADD for
Hi Pan,
all in all LGTM. Just insignificant nits.
> +void
> +expand_vec_usadd (rtx op_0, rtx op_1, rtx op_2, machine_mode vec_mode)
> +{
> + emit_vec_saddu (op_0, op_1, op_2, BINARY_OP, vec_mode);
> +}
> +
Do we really need this function? Or do you want it to be a dispatcher
for later? If it
From: Pan Li
Update in v6:
* Rebase upstream for conflict.
Log for v5:
The patch implement the SAT_ADD in the riscv backend as the
sample for both the scalar and vector. Given below vector
as example:
void vec_sat_add_u64 (uint64_t *out, uint64_t *x, uint64_t *y, unsigned n)
{
unsigned i;
