On 12/20/23 20:50, juzhe.zh...@rivai.ai wrote:
+ (and:VI
+ (match_operand:VI 3 "register_operand" "vr, vr, vr, vr")
+ (not:VI (match_operand:VI 4 "register_operand" "vr, vr, vr, vr")))
This order should be swapped like ARM SVE:
(define_expand "@cond_bic"
[(se
erand"))
(match_operand:SVE_FULL_I 4 "aarch64_simd_reg_or_zero")]
UNSPEC_SEL))]
"TARGET_SVE"
)
Otherwise, LGTM. But I'd like to expect Kito chime in.
Thanks.
juzhe.zh...@rivai.ai
From: Feng Wang
Date: 2023-12-21 10:48
To: gcc-patches
CC: kito.cheng; jeffreyalaw;
Patch v5: Add vec_duplicate operator. Make report riscv.exp with
"riscv-sim/-march=rv64gc/-mabi=lp64d/-mcmodel=medlow" is passed.
Patch v4: Add process of SEW=64 in RV32 system.
Patch v3: Moidfy constrains for crypto vector.
Patch v2: Add crypto vector ins into RATIO attr and use vr as
destinatio
