On Tue, Feb 8, 2022 at 4:35 AM Maciej W. Rozycki wrote:
> gcc/
> * config/riscv/riscv.md (UNSPEC_FMIN, UNSPEC_FMAX): New
> constants.
> (fmin3, fmax3): New insns.
> ...
I tried testing on some of the hardware I have. Both the HiFive Unleashed
(2018) and HiFive U
As at r2.2 of the RISC-V ISA specification[1] (equivalent to version 2.0
of the "F" and "D" standard architecture extensions for single-precision
and double-precision floating-point respectively) the FMIN and FMAX
machine instructions fully match our requirement for the `fminM3' and
`fmaxM3' st
