Re: [PATCH v3 09/11] riscv: thead: Add support for the XTheadMemPair ISA extension

2023-02-24 Thread Kito Cheng via Gcc-patches
Could you move those thead_* and th_* functions into thead.cc > +static bool > +thead_mempair_operand_p (rtx mem, machine_mode mode) > +{ > + if (!MEM_SIZE_KNOWN_P (mem)) > +return false; > + > + /* Only DI or SI mempair instructions exist. */ add gcc_assert (mode == SImode || mode == DImo

Re: [PATCH v3 09/11] riscv: thead: Add support for the XTheadMemPair ISA extension

2023-02-24 Thread Christoph Müllner
On Fri, Feb 24, 2023 at 10:01 AM Kito Cheng wrote: > > Got one fail: > > FAIL: gcc.target/riscv/xtheadmempair-1.c -O2 scan-assembler-times > th.luwd\t 4 > > It should scan lwud rather than luwd? Yes, this should be th.lwud. Must have been introduced after testing. I also ran the whole patchs

Re: [PATCH v3 09/11] riscv: thead: Add support for the XTheadMemPair ISA extension

2023-02-24 Thread Kito Cheng via Gcc-patches
Got one fail: FAIL: gcc.target/riscv/xtheadmempair-1.c -O2 scan-assembler-times th.luwd\t 4 It should scan lwud rather than luwd?

[PATCH v3 09/11] riscv: thead: Add support for the XTheadMemPair ISA extension

2023-02-23 Thread Christoph Muellner
From: Christoph Müllner The XTheadMemPair ISA extension allows to pair two loads or stores: * th.ldd (2x LD) * th.lwd (2x LW) * th.lwud (2x LWU) * th.sdd (2x SD) * th.swd (2x SW) The displacement of these instructions is quite limited: * Displacement := imm2 << shamt * imm2 is a 2-bit unsigned v