o.cheng' ; Wang, Yanzhang
Subject: RE: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
Update the PATCH V4 as below, sorry for missed the v4 prefix in subject.
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/620879.html
Pan
From: Li, Pan2
Sent: Wednesday, June 7, 2023 2:
;>; gcc-patches
mailto:gcc-patches@gcc.gnu.org>>
Cc: Kito.cheng mailto:kito.ch...@sifive.com>>; Li, Pan2
mailto:pan2...@intel.com>>; Wang, Yanzhang
mailto:yanzhang.w...@intel.com>>
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
HI,
+ (VNx1SF &q
Thanks JuZhe, make sense, will update the V4 for this change.
Pan
From: juzhe.zh...@rivai.ai
Sent: Wednesday, June 7, 2023 12:21 PM
To: Li, Pan2 ; gcc-patches
Cc: Kito.cheng ; Li, Pan2 ; Wang,
Yanzhang
Subject: Re: [PATCH v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
HI,
+ (VNx1SF
mp; TARGET_MIN_VLEN > 32")
+ (VNx32SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
Add TARGET_VECTOR_ELEN_FP_32 here, for FP16->FP32 conversion,
we need both ELEN_FP16 and ELEN_FP32 enable.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-07 11:00
To: gcc-
From: Pan Li
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. The related define_insn and iterator will take the
requirement based on the ZVFHMIN and ZVFH.
Please note the ZVFH will cover the ZVFHMIN instructions. This patch
add one test for this.
Signed-off-by: P
