To: Li, Pan2
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com;
rguent...@suse.de
Subject: Re: [PATCH v3] RISC-V: Bugfix for rvv bool mode precision adjustment
pan2...@intel.com writes:
> From: Pan Li
>
> Fix the bug of the rvv bool mode precision
pan2...@intel.com writes:
> From: Pan Li
>
> Fix the bug of the rvv bool mode precision with the adjustment.
> The bits size of vbool*_t will be adjusted to
> [1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The
> adjusted mode precison of vbool*_t will help unde
...@suse.de;
richard.sandif...@arm.com
Subject: Re: [PATCH v3] RISC-V: Bugfix for rvv bool mode precision adjustment
Thanks!
RISC-V part is LGTM, and I would like to wait for Richard Sandiford to say OK
to the genmodes.cc part :)
On Fri, Mar 3, 2023 at 10:31 AM wrote:
>
> From: Pan Li
>
>
Thanks!
RISC-V part is LGTM, and I would like to wait for Richard Sandiford to
say OK to the genmodes.cc part :)
On Fri, Mar 3, 2023 at 10:31 AM wrote:
>
> From: Pan Li
>
> Fix the bug of the rvv bool mode precision with the adjustment.
> The bits size of vbool*_t will be adjus
From: Pan Li
Fix the bug of the rvv bool mode precision with the adjustment.
The bits size of vbool*_t will be adjusted to
[1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The
adjusted mode precison of vbool*_t will help underlying pass to
make t
