Re: [PATCH v2 2/2] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD

On 11/4/24 6:09 AM, Craig Blackmore wrote: For fast unaligned access targets, by pieces uses up to UNITS_PER_WORD size pieces resulting in more store instructions than needed. For example gcc.target/riscv/rvv/base/setmem-2.c:f1 built with `-O3 -march=rv64gcv -mtune=thead-c906`: ``` f1:

[PATCH v2 2/2] RISC-V: Disable by pieces for vector setmem length > UNITS_PER_WORD

For fast unaligned access targets, by pieces uses up to UNITS_PER_WORD size pieces resulting in more store instructions than needed. For example gcc.target/riscv/rvv/base/setmem-2.c:f1 built with `-O3 -march=rv64gcv -mtune=thead-c906`: ``` f1: vsetivlizero,8,e8,mf2,ta,ma vm