On 12/05/2020 23:33, Jim Wilson wrote:
> On Mon, Apr 27, 2020 at 10:08 AM Craig Blackmore
> wrote:
>> Thanks for the review. I have updated the following patch with those changes.
> This looks good, and the tree is open for development work again, so I
> committed both parts 1 and 2 and pushed it.
On Mon, Apr 27, 2020 at 10:08 AM Craig Blackmore
wrote:
> Thanks for the review. I have updated the following patch with those changes.
This looks good, and the tree is open for development work again, so I
committed both parts 1 and 2 and pushed it.
One weird thing is that while the patch progr
On 08/04/2020 17:04, Jim Wilson wrote:
> On Wed, Feb 19, 2020 at 3:40 AM Craig Blackmore
> wrote:
>> On 10/12/2019 18:28, Craig Blackmore wrote:
>> Thank you for your review. I have posted an updated patch below which I think
>> addresses your comments.
>>
>> Ping
>>
>> https://gcc.gnu.org/ml/gcc
On Wed, Feb 19, 2020 at 3:40 AM Craig Blackmore
wrote:
> On 10/12/2019 18:28, Craig Blackmore wrote:
> Thank you for your review. I have posted an updated patch below which I think
> addresses your comments.
>
> Ping
>
> https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00712.html
This looks OK. The
On 10/12/2019 18:28, Craig Blackmore wrote:
>
> Hi Jim,
>
> Thank you for your review. I have posted an updated patch below which I think
> addresses your comments.
>
Ping
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00712.html
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00713.html
Craig
Hi Jim,
Thank you for your review. I have posted an updated patch below which I think
addresses your comments.
On 30/10/2019 23:57, Jim Wilson wrote:
> On Fri, Oct 25, 2019 at 10:40 AM Craig Blackmore
> wrote:
>> This patch aims to allow more load/store instructions to be compressed by
>> replac
ce: +972-4-9078756
>> Mobile: +972-50-8867756
>>
>>> -Original Message-
>>> From: Jim Wilson
>>> Sent: Thursday, 31 October 2019 1:57
>>> To: Craig Blackmore
>>> Cc: GCC Patches ; Ofer Shinaar
>>> ; Nidal Faour ; Kito Cheng
..@wdc.com
> Office: +972-4-9078756
> Mobile: +972-50-8867756
>
> >-Original Message-
> >From: Jim Wilson
> >Sent: Thursday, 31 October 2019 1:57
> >To: Craig Blackmore
> >Cc: GCC Patches ; Ofer Shinaar
> >; Nidal Faour ; Kito Cheng
> >;
---Original Message-
>From: Jim Wilson
>Sent: Thursday, 31 October 2019 1:57
>To: Craig Blackmore
>Cc: GCC Patches ; Ofer Shinaar
>; Nidal Faour ; Kito Cheng
>; Jeff Law
>Subject: Re: [PATCH v2 1/2] RISC-V: Add shorten_memrefs pass
>
>CAUTION: This email originat
FYI the testcase I'm using to test the patch. Some of the functions
get smaller, some of them get bigger, and some don't change in size
but should when compiled for an rv64 target.
Jim
void
store1z (int *array)
{
array[200] = 0;
array[201] = 0;
array[202] = 0;
array[203] = 0;
}
void
stor
On Fri, Oct 25, 2019 at 10:40 AM Craig Blackmore
wrote:
> This patch aims to allow more load/store instructions to be compressed by
> replacing a load/store of 'base register + large offset' with a new load/store
> of 'new base + small offset'. If the new base gets stored in a compressed
> registe
On Sat, 2019-10-26 at 14:04 -0600, Jeff Law wrote:
> On 10/26/19 1:33 PM, Andrew Waterman wrote:
> > I don't know enough to say whether the legitimize_address hook is
> > sufficient for the intended purpose, but I am sure that RISC-V's
> > concerns are not unique: other GCC targets have to cope wit
On 10/26/19 1:33 PM, Andrew Waterman wrote:
> I don't know enough to say whether the legitimize_address hook is
> sufficient for the intended purpose, but I am sure that RISC-V's
> concerns are not unique: other GCC targets have to cope with
> offset-size constraints that are coupled to register-al
On 10/26/19 1:10 PM, Oleg Endo wrote:
> On Sat, 2019-10-26 at 12:21 -0600, Jeff Law wrote:
>> On 10/25/19 11:39 AM, Craig Blackmore wrote:
>>> This patch aims to allow more load/store instructions to be
>>> compressed by
>>> replacing a load/store of 'base register + large offset' with a new
>>> lo
I don't know enough to say whether the legitimize_address hook is
sufficient for the intended purpose, but I am sure that RISC-V's
concerns are not unique: other GCC targets have to cope with
offset-size constraints that are coupled to register-allocation
constraints.
On Sat, Oct 26, 2019 at 11:2
On Sat, 2019-10-26 at 12:21 -0600, Jeff Law wrote:
> On 10/25/19 11:39 AM, Craig Blackmore wrote:
> > This patch aims to allow more load/store instructions to be
> > compressed by
> > replacing a load/store of 'base register + large offset' with a new
> > load/store
> > of 'new base + small offset'
On 10/25/19 11:39 AM, Craig Blackmore wrote:
> This patch aims to allow more load/store instructions to be compressed by
> replacing a load/store of 'base register + large offset' with a new load/store
> of 'new base + small offset'. If the new base gets stored in a compressed
> register, then the
This patch aims to allow more load/store instructions to be compressed by
replacing a load/store of 'base register + large offset' with a new load/store
of 'new base + small offset'. If the new base gets stored in a compressed
register, then the new load/store can be compressed. Since there is an o
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