On 3/20/25 3:31 AM, Yixuan Chen wrote:
Hi Majin,
Thanks for your suggestion,
Look like the document don't contain the following tune information:
/* fmv_cost */, /* vector_unaligned_access */, /* use_divmod_expansion
*/, and /* overlap_op_by_pieces */
, I will follow your further modificat
Hi Majin,
Thanks for your suggestion,
Look like the document don't contain the following tune information:
/* fmv_cost */, /* vector_unaligned_access */, /* use_divmod_expansion */,
and /* overlap_op_by_pieces */
, I will follow your further modification and wait for the gcc16 window to
send the
On Mon, 17 Mar 2025 17:31:36 +0800, Yixuan Chen wrote:
> gcc/ChangeLog:
>
> * config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c910.
> (RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.
> * config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info.
>
On 3/17/25 3:31 AM, Yixuan Chen wrote:
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c910.
(RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.
* config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info.
* doc/invoke.te
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add xt-c908, xt-c910.
(RISCV_CORE): Add xt-c908, xt-c910 and xt-c920v1 and xt-c920v2.
* config/riscv/riscv.cc: Add xt-c908, xt-c910 tune info.
* doc/invoke.texi: Add xt-c908, xt-c910 and xt-c920v1 and xt-c9
