> On 12 Nov 2024, at 4:27 PM, Richard Sandiford
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> Soumya AR writes:
>> diff --git a/gcc/config/aarch64/aarch64-sve.md
>> b/gcc/config/aarch64/aarch64-sve.md
>> index 06bd3e4bb2c..119a0e53853 100644
>> --- a/gcc/confi
Soumya AR writes:
> diff --git a/gcc/config/aarch64/aarch64-sve.md
> b/gcc/config/aarch64/aarch64-sve.md
> index 06bd3e4bb2c..119a0e53853 100644
> --- a/gcc/config/aarch64/aarch64-sve.md
> +++ b/gcc/config/aarch64/aarch64-sve.md
> @@ -5088,6 +5088,21 @@
> ;; - FTSSEL
> ;; --
Hi Richard,
> On 7 Nov 2024, at 3:19 PM, Richard Sandiford
> wrote:
>
> External email: Use caution opening links or attachments
>
>
> Soumya AR writes:
>> Changes since v1:
>>
>> This revision makes use of the extended definition of aarch64_ptrue_reg to
>> generate predicate registers wi
Soumya AR writes:
> Changes since v1:
>
> This revision makes use of the extended definition of aarch64_ptrue_reg to
> generate predicate registers with the appropriate set bits.
>
> Earlier, there was a suggestion to add support for half floats as well. I
> extended the patch to include HFs but G
Changes since v1:
This revision makes use of the extended definition of aarch64_ptrue_reg to
generate predicate registers with the appropriate set bits.
Earlier, there was a suggestion to add support for half floats as well. I
extended the patch to include HFs but GCC still emits a libcall for ld
