Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-09 Thread Vineet Gupta
Hi Robin, On 4/8/25 21:56, Robin Dapp wrote: Yay ! It does work. Awesome. I've uploaded the further reduced test to PR/119533 >>> Hmm, I'm seeing the same ICE as before with my patch. Did you happen >>> to change >>> something else on your local tree still? Ye

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Robin Dapp
On 4/8/25 16:32, Vineet Gupta wrote: Yay ! It does work. Awesome. I've uploaded the further reduced test to PR/119533 Hmm, I'm seeing the same ICE as before with my patch. Did you happen to change something else on your local tree still? Yeah I had some debug stuff lying around. In particular

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Vineet Gupta
On 4/8/25 16:32, Vineet Gupta wrote: >> Yay ! It does work. Awesome. >> I've uploaded the further reduced test to PR/119533 > Hmm, I'm seeing the same ICE as before with my patch. Did you happen to > change > something else on your local tree still? >> Yeah I had some debug s

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Vineet Gupta
On 4/8/25 13:47, Vineet Gupta wrote: > On 4/8/25 12:27, Robin Dapp wrote: > Yay ! It does work. Awesome. > I've uploaded the further reduced test to PR/119533 Hmm, I'm seeing the same ICE as before with my patch. Did you happen to change something else on your local tree s

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Vineet Gupta
On 4/8/25 12:27, Robin Dapp wrote: Yay ! It does work. Awesome. I've uploaded the further reduced test to PR/119533 >>> Hmm, I'm seeing the same ICE as before with my patch. Did you happen to >>> change >>> something else on your local tree still? Yeah I had some debug stuff lying aro

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Robin Dapp
Yay ! It does work. Awesome. I've uploaded the further reduced test to PR/119533 Hmm, I'm seeing the same ICE as before with my patch. Did you happen to change something else on your local tree still? On top, I'm now seeing a ton of vsetvl test failures vs just the one I reported... No ide

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Robin Dapp
Yay ! It does work. Awesome. I've uploaded the further reduced test to PR/119533 Hmm, I'm seeing the same ICE as before with my patch. Did you happen to change something else on your local tree still? On top, I'm now seeing a ton of vsetvl test failures vs just the one I reported... No ide

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Robin Dapp
Yay ! It does work. Awesome. I've uploaded the further reduced test to PR/119533 Hmm, I'm seeing the same ICE as before with my patch. Did you happen to change something else on your local tree still? -- Regards Robin

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Vineet Gupta
On 4/8/25 02:12, Robin Dapp wrote: >> However we still see lift up using those blocks - the earliest set computed >> contained the supposedly elided bbs. >> >>   Try lift up 0. >> >>   earliest: >>     Edge(bb 16 -> bb 17): n_bits = 3, set = {1 } >> >>   Try lift up 1. >> >>

Re: vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-08 Thread Robin Dapp
Hi Vineet, However we still see lift up using those blocks - the earliest set computed contained the supposedly elided bbs.   Try lift up 0.   earliest:     Edge(bb 16 -> bb 17): n_bits = 3, set = {1 }   Try lift up 1.   earliest:     Edge(bb 15 -> bb

vsetvl abormal edge (was Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533])

2025-04-07 Thread Vineet Gupta
On 3/31/25 21:54, Jeff Law wrote: > And if that's the case then you can't simply skip an abnormal edge. You > have to do something sensible. > > That "something sensible" has traditionally been to ensure there is > never a need propagated to an edge since you can't insert on an abnormal > criti

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-04-05 Thread Vineet Gupta
On 4/1/25 17:44, Jeff Law wrote: > On 4/1/25 12:15 PM, Vineet Gupta wrote: >> On 3/31/25 23:48, Heinrich Schuchardt wrote: >>> On 3/30/25 01:49, Vineet Gupta wrote: changes since v2 - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It h

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-04-05 Thread Vineet Gupta
On 3/29/25 17:58, Jeff Law wrote: > On 3/29/25 6:49 PM, Vineet Gupta wrote: >> changes since v2 >> - dump log sanfu >> >> --- >> vsetvl phase4 uses LCM guided info to insert VSETVL insns. >> It has an additional loop to insert missing vsetvls on certain edges. >> Currently it asserts/aborts on en

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-04-04 Thread Heinrich Schuchardt
On 3/30/25 01:49, Vineet Gupta wrote: changes since v2 - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It has an additional loop to insert missing vsetvls on certain edges. Currently it asserts/aborts on encountering EDGE_ABNORMAL. When enabling go frontend with

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-04-01 Thread Jeff Law
On 4/1/25 10:46 PM, Heinrich Schuchardt wrote: On 4/1/25 20:15, Vineet Gupta wrote: On 3/31/25 23:48, Heinrich Schuchardt wrote: On 3/30/25 01:49, Vineet Gupta wrote: changes since v2    - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It has an additional lo

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-04-01 Thread Heinrich Schuchardt
On 4/1/25 20:15, Vineet Gupta wrote: On 3/31/25 23:48, Heinrich Schuchardt wrote: On 3/30/25 01:49, Vineet Gupta wrote: changes since v2 - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It has an additional loop to insert missing vsetvls on certain edges. Curr

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-04-01 Thread Jeff Law
On 4/1/25 12:15 PM, Vineet Gupta wrote: On 3/31/25 23:48, Heinrich Schuchardt wrote: On 3/30/25 01:49, Vineet Gupta wrote: changes since v2 - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It has an additional loop to insert missing vsetvls on certain edges

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-04-01 Thread Vineet Gupta
On 3/31/25 23:48, Heinrich Schuchardt wrote: > On 3/30/25 01:49, Vineet Gupta wrote: >> changes since v2 >> - dump log sanfu >> >> --- >> vsetvl phase4 uses LCM guided info to insert VSETVL insns. >> It has an additional loop to insert missing vsetvls on certain edges. >> Currently it asserts/abo

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-03-31 Thread Jeff Law
On 3/31/25 1:33 PM, Vineet Gupta wrote: On 3/29/25 17:58, Jeff Law wrote: On 3/29/25 6:49 PM, Vineet Gupta wrote: changes since v2 - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It has an additional loop to insert missing vsetvls on certain edges. Current

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-03-31 Thread Jeff Law
On 3/31/25 3:43 PM, Vineet Gupta wrote: But what state is in play that caused it to want to insert something? That's what needs to be understood here. I don't see anything in bb64 that requires vsetvl to be in any particular state. So why did vsetvl insertion think that it needed to insert

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-03-31 Thread Vineet Gupta
On 3/31/25 12:39, Jeff Law wrote: * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): skip EDGE_ABNORMAL. gcc/testsuite/ChangeLog: * go.dg/pr119533-riscv.go: New test. >>> So presumably it wants to insert on the EH edge for a reason. Just >>> skipping t

Re: [PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-03-29 Thread Jeff Law
On 3/29/25 6:49 PM, Vineet Gupta wrote: changes since v2 - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It has an additional loop to insert missing vsetvls on certain edges. Currently it asserts/aborts on encountering EDGE_ABNORMAL. When enabling go frontend

[PATCH v2] RISC-V: vsetvl: skip abnormal edge on vsetvl insertion [PR119533]

2025-03-29 Thread Vineet Gupta
changes since v2 - dump log sanfu --- vsetvl phase4 uses LCM guided info to insert VSETVL insns. It has an additional loop to insert missing vsetvls on certain edges. Currently it asserts/aborts on encountering EDGE_ABNORMAL. When enabling go frontend with V enabled, libgo build hits the assert.