Committed, thanks Juzhe and Kito.
Pan
-Original Message-
From: Kito Cheng
Sent: Friday, June 9, 2023 4:28 PM
To: juzhe.zh...@rivai.ai
Cc: Li, Pan2 ; gcc-patches ; Robin
Dapp ; jeffreyalaw ; Wang, Yanzhang
Subject: Re: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN
lgtm too, thanks :)
On Fri, Jun 9, 2023 at 3:15 PM juzhe.zh...@rivai.ai
wrote:
>
> LGTM.
>
>
>
> juzhe.zh...@rivai.ai
>
> From: pan2.li
> Date: 2023-06-09 15:07
> To: gcc-patches
> CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
> S
LGTM.
juzhe.zh...@rivai.ai
From: pan2.li
Date: 2023-06-09 15:07
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN.
From: Pan Li
This patch would like to refactor the requirement
From: Pan Li
This patch would like to refactor the requirement of both the ZVFH
and ZVFHMIN. By default, the ZVFHMIN will enable FP16 for all the
iterators of RVV. And then the ZVFH will leverage one define attr as
the gate for FP16 supported or not.
Please note the ZVFH will cover the ZVFHMIN i
