RE: [PATCH v1 2/2] RISC-V: Add testcases for form 3 of signed vector SAT_ADD

...@rivai.ai; kito.ch...@gmail.com; jeffreya...@gmail.com; Robin Dapp Subject: Re: [PATCH v1 2/2] RISC-V: Add testcases for form 3 of signed vector SAT_ADD LGTM (in case you haven't committed it yet). -- Regards Robin

Re: [PATCH v1 2/2] RISC-V: Add testcases for form 3 of signed vector SAT_ADD

LGTM (in case you haven't committed it yet). -- Regards Robin

[PATCH v1 2/2] RISC-V: Add testcases for form 3 of signed vector SAT_ADD

From: Pan Li Form 3: #define DEF_VEC_SAT_S_ADD_FMT_3(T, UT, MIN, MAX) \ void __attribute__((noinline)) \ vec_sat_s_add_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ {