Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3

On 8/27/24 1:17 AM, pan2...@intel.com wrote: From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_SUB IMM form 3. Aka: Form 3: #define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \

[PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3

From: Pan Li This patch would like to add test cases for the unsigned scalar .SAT_SUB IMM form 3. Aka: Form 3: #define DEF_SAT_U_SUB_IMM_FMT_3(T, IMM) \ T __attribute__((noinline)) \ sat_u_sub_imm##IMM##_##T##_fmt_3 (T y) \ { \ retu